LPC 23XX- TIMER

M3: Embedded Architectures- 2: ARM based LPC23xx

Features
• Four Timer/Counters
• 4 channels/Timer
• A minimum of 2 capture i/ps & 2 Match o/ps are pinned out for all 4
timers
• Choice of several pins for each
• 32 bit Timer/Counter with programmable 32 bit Prescaler
• Counter / Timer operation

RL4.1.4 Embedded System Design © K.R.Anupama &

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Example
• Program LPC 23xx to count the no. of objects crossing a particular
point within a period of 1 second. Also find the time interval
between two objects

RL4.1.4 Embedded System Design © K.R.Anupama &

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INPUT CAPTURE

RL4.1.4 Embedded System Design © K.R.Anupama &

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Channel 0 CAP0.0

Channel 1 CAP0.1

Channel 2
Channel 3

Timer 0

RL4.1.4 Embedded System Design © K.R.Anupama &

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 Input Capture EDGB:EDGA
CLK
000A
0005
32-bit Counter
H PT
Edge
000A
0005HReg
Capture Detector

CF

CI Interrupt Logic

Interrupt Request

RL4.1.4 Embedded System Design © K.R.Anupama &

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Program for Input Capture
Turn on Timer 0/1/2/3
PCONP
Bit1 :PCTIM0
Enabled on Reset
Bit2 :PCTIM1
Bit22 :PCTIM2
Bit23 :PCTIM3

PINSEL Registers

RL4.1.4 Embedded System Design © K.R.Anupama &

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Input Capture 0.0 P1.26 AltF3, P3.23 AltF2
Input Capture 0.1 P1.27 AltF3, P3.24 AltF2

Input Capture 1.0 P1.18 AltF3

Input Capture 1.1 P1.19 AltF3

Input Capture 2.0 P0.4 AltF3

Input Capture 2.1 P0.5 AltF3

Input Capture 3.0 P0.23 AltF3

Input Capture 3.1 P0.24 AltF3

RL4.1.4 Embedded System Design © K.R.Anupama &

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Program for Input Capture
Clock for Timer 0/1/2/3
PCLK Selection Register 0
0 0 CCLK/4
Bit2-3 :PCLK_TIMER0
Bit4-5 :PCLK_TIMER1 0 1 CCLK

PCLK Selection Register 1

1 0 CCLK/2
Bit12-13 :PCLK_TIMER2
Bit14-15 :PCLK_TIMER3 1 1 CCLK/8

RL4.1.4 Embedded System Design © K.R.Anupama &

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Program for Input Capture
Pre Scale for Timer 0/1/2/3
TxPR
TxPC
TxC

RL4.1.4 Embedded System Design © K.R.Anupama &

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Select Clock for Timer/Counter
Counter Control Register for Timer 0/1/2/3
CCxR

CIS1 CIS0 CM1 CMO

CAP x.0 0 0 0 0 Rising Edge
PCLK
CAP x.1 1 0 0 1 Rising edge
CAP
Resv 0 1 1 0 Falling edge
CAP
Resv 1 1 1 1 Both edges
CAP
RL4.1.4 Embedded System Design © K.R.Anupama &
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 PCLK SEL 0:1 CPR

1/2/4/8 Pre-Scale+1
CCLK

Counter
CAP

CCR

RL4.1.4 Embedded System Design © K.R.Anupama &

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Program for Input Capture
Capture Registers for Timer 0/1/2/3
TxCCR

CA1I CAP1FE CAP1RE CA0I CAP0FE CAP0RE

Program Interrupt Unit

RL4.1.4 Embedded System Design © K.R.Anupama &

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Program for Input Capture
TxCR

TR TE

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Program for Input Capture
TxIR

IC3 IC2 IC1 IC0 IM3 IM2 IM1 IM0

Ack Interrupt

RL4.1.4 Embedded System Design © K.R.Anupama &

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Program for Input Capture
Capture Registers for Timer 0/1/2/3
TxCR0-TxCR3

RL4.1.4 Embedded System Design © K.R.Anupama &

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OUTPUT COMPARE

RL4.1.4 Embedded System Design © K.R.Anupama &

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Features
4 32 bit match registers that allow
Continuous op with optional int generation on match
Stop timer on match with optional int generation
Reset timer on match with optional int generation
Up to 4 external o/ps corresponding to match regs
Set low on match
Set high on match
Toggle on match
Do nothing on match

RL4.1.4 Embedded System Design © K.R.Anupama &

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 Output Compare Reset/Continue/Stop
on Match
CLK
32-bit
0005
0004
0003
0002
0000
0001
counter
OL0
OL1 PT
PTx
32-bit comparator CF Logic

Match
0005Reg

CI INT
Logic

RL4.1.4 Embedded System Design © K.R.Anupama &

Interrupt
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Output Compare 0.0 P1.28 AltF3, P3.25 AltF2
Output Compare 0.1 P1.29 AltF3, P3.26 AltF2

Output Compare 1.0 P1.22 AltF3

Output Compare 1.1 P1.25 AltF3

Output Compare 2.0 P0.6 AltF3, P4.28 AltF2

Output Compare 2.1 P0.7 AltF3, P4.29 AltF2
Output Compare 2.2 P0.8 AltF3
Output Compare 2.3 P0.9 AltF3

Output Compare 3.0 P0.10 AltF3

Output Compare 3.1 P0.11 AltF
RL4.1.4 Embedded System Design © K.R.Anupama &
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 Program for Output Compare
Match Registers for Timer 0/1/2/3
TxMR0-TxMR3
TxMCR

MR2S MR2R MR2I MR1S MR1R MR1I MR0S MR0R MR0I

MR3S MR3R MR3I

RL4.1.4 Embedded System Design © K.R.Anupama &

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 Program for Output Compare
External Match Registers for Timer 0/1/2/3
TxEMCR

EMC1 EMC0 EM3 EM2 EM1 EMO

EMC3 EMC2

RL4.1.4 Embedded System Design © K.R.Anupama &

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Program LPC 23xx to count the no. of
objects crossing a particular point within a
period of 1 second. Also find the time
interval between two objects.

RL4.1.4 Embedded System Design © K.R.Anupama &

23
Meetha.V.shenoy