ARM- Exceptions

M3: Embedded Architectures- 1: RISC Architecture - ARM

ARM-Exceptions
• Handled by entering into different operating modes
• Exception Entry
 Preserves the address of next instruction into LR

RL 3.3.1 Embedded System Design © K.R.Anupama &

 Copies the CPSR into SPSR
 CPSR modes bits set to appropriate operating mode

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Interrupts/ Address Entry F I
Exceptions Mode
Reset 0x 0000 0000 Supervisor 1 1
Undefined 0x 0000 0004 Undefined U 1
SWI 0x 0000 0008 Supervisor U 1
Pre-fetch 0x 0000 000C Abort U 1

RL 3.3.1 Embedded System Design © K.R.Anupama &

Abort
Data Abort 0x 0000 0010 Abort U 1
IRQ 0x 0000 0018 IRQ U 1
FIQ 0x 0000 001C FIQ 1 1

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Main Program
ADR r4,a
LDR r0,[r4]
LDR r4,[r2] FIQ
LDR r1,[r4]
ADD r3,r0,r1
r15 r14_fiq
CPSR SPSR_fiq
CPSR (Mode) - FIQ
Enters FIQ

RL 3.3.1 Embedded System Design © K.R.Anupama &

r14_fiq - 4 r15
SPSR_fiq CPSR

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 r0
r1
r2
r3
r4
r5
r6
r7

RL 3.3.1 Embedded System Design © K.R.Anupama &

r8 r8_fiq
r9 r9_fiq
r10 r10_fiq
r11
r11_fiq
r12 LR_FIQ
r12_fiq
r13
back-up r13_fiq

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r14
r15(PC) r14_fiq
CPSR
back-up

SPSR_FIQ SPSR_fiq
User FIQ 5
FIQ
• nFIQ pin –low
• Why FIQ – all high regs are banked – reduces int latencies
• ARM checks for low level at the end of each instruction

RL 3.3.1 Embedded System Design © K.R.Anupama &

• FIQ – disabled in privileged mode – F -1

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FIQ - actions
• Actions Taken on FIQ
• R14_fiq = Address of next inst to be executed +4
• SPSR_fiq = CPSR

RL 3.3.1 Embedded System Design © K.R.Anupama &

• CPSR[4:0] = FIQ mode
• T bit = 0 F = 1 I=1
• PC = Address of FIQ ISR

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• Exit From FIQ
• SUBS PC, R14,#4

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IRQ
• nIRQ pin –low

• Actions Taken on IRQ

RL 3.3.1 Embedded System Design © K.R.Anupama &

• R14_irq = Address of next inst to be executed +4
• SPSR_irq = CPSR
• CPSR[4:0] = IRQ mode
• T bit = 0 I = 1
• PC = Address of IRQ ISR

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• Exit From IRQ
• SUBS PC, R14,#4

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Supervisor Mode
• Entry-SWI
• Actions Taken on SWI
• R14_svc = Address of SWI + 4

RL 3.3.1 Embedded System Design © K.R.Anupama &

• SPSR_svc = CPSR
• CPSR[4:0] = Supervisor mode
• T bit = 0 I=1
• PC = Address of Supervisor Routine

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• Exit From Supervisor
• MOVS PC, R14

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Undefined
• Inst than cannot be handled by ARM/co-processor
• Actions Taken on Undefined
• R14_und = Address of Instruction + 4

RL 3.3.1 Embedded System Design © K.R.Anupama &

• SPSR_und = CPSR
• CPSR[4:0] = Undefined mode
• T bit = 0 I=1
• PC = Address of Undefined Routine

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• Exit From Undefined
• MOVS PC, R14

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