COE 485 Sem 1, 2023

Advanced Computer Architecture

Multicycle Datapath
 Review
• Construction of the Datapath
– Determine instruction types
• R-format
• Conditional Branch
• Unconditional Branch
• Load/store
– Develop datapath modules (RF, ALU, Memory, SignExt)
– Connect modules to form composite datapath
• Single-Cycle Datapath
– All instructions take one cycle (CPI = 1)
– Cycle time dictated by circuit settling time
– All operations take time of slowest operation (load)
What’s wrong with single cycle?
Instructions Cycles Time
X X
Program Instruction Cycle
(code size) (CPI) (cycle time)
• Critical path probably lw:
– I-mem, reg-read, alu, d-mem, reg-write
• Other instructions faster
– E.g. rrr: skip d-mem
• Instruction variation much worse for full ISA and
real implementation:
– FP divide
– Cache misses
 Single Cycle Implementation
• Solution
– Variable clock?
• Too hard to control, design
– Fixed short clock
• Variable cycles per instruction
Overview – Multicycle Datapath
• Each instruction has multiple stages
• Each stage takes one cycle
1. Instruction fetch All instructions use these
2. Instruction decode / Data fetch
3. ALU ops / R-format execution
4. R-format completion
5. Memory access completion
Each stage can re-use hardware from previous stage
efficient use of hardware and time
>> New Hardware required to buffer stage output
>> New Muxes required for hardware re-use
>> Expanded Control for new hardware
 Recall: Simple Datapath

Instruction rd Data
memory
rs Address
PC

Address Registers ALU

rt Data
Instruction memory

+4 Data
imm
Opcode,
funct
Controller

° Datapath is based on register transfers required to execute instructions

° Control causes the right transfers to happen
 Recall: R-format Datapath
• Format: opcode r3, r1, r2
ALU op
Register File 3

Read Reg 1 Read

Instruction Zero
Read Reg 2 Data 1

Write ALU
Register Read
Write Data Data 2
Result
Register
Write
Recall: Load/Store Datapath

Fetch Decode Execute

Recall: Branch Datapath

Fetch Decode Execute

 Hi-Level View: Multicycle DP

Instr. Fetch Instr. Decode/Data Fetch Execute

 Hi-Level View: Multicycle DP
How do we make multicycle datapath (DP)???
1. Replace 3 ALUs from the single-cycle DP with one ALU
2. Add one multiplexer to select ALU input
3. Add one control line for the ALU input multiplexer
• New inputs: Constant = 4 [PC + 4]
• Sign-ext., shifted offset
[BTA calc.]
4. Add temporary (buffer) registers: (storage betw.cycles)
• MDR: Memory Data Register
• IR: Instruction Register
• A,B: ALU operand registers
• ALUout: ALU output register
 Multi-cycle Implementation
• Control is more complex
Multi-cycle Ctrl Signals
 Making Sense of Multicycle DP
Step 1: Decompose the MC/DP execution sequence into cycles
Step 2: Examine which cycles apply to which instructions
One-Cycle Steps R-fmt lw sw beq j
1. Instruction Fetch
2. Instruction Decode
3. ALU ops / R-format Execution
4. R-format Completion/Mem Access
5. Data Read Completion
 Multicycle DP: R-format
Step 1: Fetch instr. // Store in IR // Compute PC + 4
Step 2: Decode instruction: opcode, rd, rs, rt, funct fields
Data fetch: Apply rs, rt to Register File
Data Read into A,B buffer registers
(ALUin)
Step 3: ALU operation (ALUsrcA, ALUsrcB, ALUop)
ALU output goes into ALUout register

Step 4: ALUout register contents written to Register File write input

Register number in rd written (Assert:
RegWrite,RegDst)
CPI for R-format = 4 cycles
 Multicycle DP: Store Word (sw)
Step 1: Fetch instr. // Store in IR // Compute PC + 4
Step 2: Decode instruction: opcode, rs, rt, offset fields
Data fetch: Apply rt to Register File => Base address
Data Read into A buffer register (Base)
SignExt,Shift offset field into B buffer
register
Step 3: ALU operation (ALUsrcB, ALUop) => Base + Offset
ALU output goes into ALUout register

Step 4: ALUout register contents applied as Memory Address

Assert: MemWrite [ALUout => RegFile]

CPI for Store = 4 cycles

 Multicycle DP: Load Word (lw)
Step 1: Fetch instr. // Store in IR // Compute PC + 4
Step 2: Decode instruction: opcode, rd, rt, offset fields
Data fetch: Apply rt to Register File => Base address
Data Read into A buffer register (Base)
SignExt,Shift offset field into B buffer
register
Step 3: ALU operation (ALUsrcB, ALUop) => Base + Offset
ALU output goes into ALUout register
Step 4: ALUout register contents applied as Memory Address
Assert: MemRead
Step 5: Memory Data Out routed to Register File write input
Register number from rd written to (Assert:
CPI for Load = 5 cycles
 Multicycle DP: Cond. Branch
Step 1: Fetch instr. // Store in IR // Compute PC + 4
Step 2: Decode instruction: opcode, rs, rt, offset fields
Data fetch: Apply rs, rt to Register File
BTA calc: SignExt,Shift offset field into B buffer
register
ALU compose PC, offset => BTA
Step 3: ALU operation (ALUsrcA, ALUsrcB, ALUop) = compare
ALU output present at Zero register causes Control
to select BTA or PC+4

CPI for Conditional Branch = 3 cycles

 Multicycle DP: Jump
Step 1: Fetch instr. // Store in IR // Compute PC + 4
Step 2: Decode instruction: opcode, address fields
JTA calc: SignExt,Shift offset field [Bits 27-0]
Concatenate with PC [Bits 31-28] =>
JTA
Step 3: PC replaced by the Jump Target Address (JTA)
PCsource = 10, PCWrite asserted

CPI for Jump = 3 cycles

 Multi-cycle Steps
Step Description Sample Actions
IF Fetch IR=MEM[PC]
PC=PC+4
ID Decode A=RF(IR[25:21])
B=RF(IR[20:16])
Target=PC+SE(IR[15:0] << 2)
EX Execute ALUout = A + SE(IR[15:0]) # lw/sw
ALUout = A op B # rrr
if (A==B) PC = target # beq
Mem Memory MEM[ALUout] = B # sw
MDR = MEM[ALUout] #lw
RF(IR[15:11]) = ALUout # rrr
WB Writeback Reg(IR[20:16]) = MDR # lw
Multi-cycle Ctrl Signals
Multicycle DP: 1-bit Ctl. Signals
Multicycle DP: 2-bit Ctl. Signals
 Implementing Control
• Value of control signals is dependent upon:
– what instruction is being executed
– which step is being performed

• Use the information we have accumulated to specify a finite state

machine
– specify the finite state machine graphically, or
– use microprogramming

• Implementation is then derived from the specification

 Review: Finite State Machines
• Finite state machines (FSMs):
– a set of states and
– next state function, determined by current state and the input
– output function, determined by current state and possibly input

Next
state
Next-state
Current state
function

Clock
Inputs

Output
Outputs
function

– We’ll use a Moore machine – output based only on current state

 Multi-cycle Control
• Function of Op[5:0] and current step
• Defined as Finite State Machine (FSM) or
– Micro-program or microcode
 Finite State Machine (FSM)
• For each state, define:
– Control signals for datapath for this cycle
– Control signals to determine next state
• All instructions start in same IF state
• Instructions terminate by making IF next
– After proper PC update, of course
 FSM Control: High-level View
Start

Instruction fetch/decode and register fetch

(Figure 5.37)

Memory access
R-type instructions Branch instruction Jump instruction
instructions
(Figure 5.39) (Figure 5.40) (Figure 5.41)
(Figure 5.38)

High-level view of FSM control

Instruction decode/
Instruction fetch Register fetch
0
MemRead 1
ALUSrcA = 0
IorD = 0
Asserted signals Start
IRWrite
ALUSrcB = 01
ALUSrcA = 0
ALUSrcB = 11
shown inside ALUOp = 00
PCWrite
ALUOp = 00

state circles PCSource = 00

)
ype

(Op = 'JMP')
')
-t

EQ
p =R

'B
') (O

=
W
= 'S

p
( Op

(O
W ') or
= 'L
( Op

Memory reference FSM R-type FSM Branch FSM Jump FSM

(Figure 5.38) (Figure 5.39) (Figure 5.40) (Figure 5.41)

Instruction fetch and decode steps of every instruction is identical

FSM Control: Memory Reference
From state 1
(Op = 'LW') or (Op = 'SW')
Memory address computation
2

ALUSrcA = 1
ALUSrcB = 10
ALUOp = 00

(O
(Op = 'LW')

p
=
'S
W
')
Memory Memory
access access
3 5

MemRead
MemWrite
IorD = 1
IorD = 1

Write-back step
4

RegWrite To state 0
MemtoReg = 1 (Figure 5.37)
RegDst = 0

FSM control for memory-reference has 4 states

FSM Control: R-type Instruction
From state 1
(Op = R-type)

Execution
6

ALUSrcA = 1
ALUSrcB = 00
ALUOp = 10

R-type completion
7
RegDst = 1
RegWrite
MemtoReg = 0

To state 0
(Figure 5.37)
FSM control to implement R-type instructions has 2 states
FSM Control: Branch Instruction
From state 1
(Op = 'BEQ')

Branch completion
8
ALUSrcA = 1
ALUSrcB = 00
ALUOp = 01
PCWriteCond
PCSource = 01

To state 0
(Figure 5.37)

FSM control to implement branches has 1 state

FSM Control: Jump Instruction

From state 1
(Op = 'J')

Jump completion
9

PCWrite
PCSource = 10

To state 0
(Figure 5.37)

FSM control to implement jumps has 1 state

 FSM Control: Complete View Instruction fetch
Instruction decode/
register fetch
0
MemRead 1
IF ALUSrcA = 0
IorD = 0 ID ALUSrcA = 0
Start IRWrite ALUSrcB = 11
ALUSrcB = 01 ALUOp = 00
ALUOp = 00
PCWrite
PCSource = 00
e)

')
-t yp

EQ

(Op = 'J')
= R

'B
(Op
W ')

=
Memory address 'S

p
p= Branch Jump

(O
computation O
or ( Execution completion completion
W ')
= 'L
2 ( Op 6 8 9
ALUSrcA = 1
ALUSrcA = 1 ALUSrcB = 00
EX
ALUSrcA =1 PCWrite
ALUSrcB = 10 ALUSrcB = 00 ALUOp = 01
ALUOp = 00 PCSource = 10
ALUOp = 10 PCWriteCond
PCSource = 01
(O
(Op = 'LW')

p
=
'S
W
')

Memory Memory
access access R-type completion
3 5 7

RegDst = 1 Labels on arcs are conditions

MEM MemRead
IorD = 1
MemWrite
IorD = 1
RegWrite
MemtoReg = 0 that determine next state

Write-back step
4

RegDst = 0
WB RegWrite
MemtoReg = 1

The complete FSM control for the multicycle MIPS datapath:

refer Multicycle Datapath with Control II
 Microprogramming
• Microprogramming is a method of specifying FSM control that resembles a
programming language – textual rather graphic
– this is appropriate when the FSM becomes very large, e.g., if the instruction set is
large and/or the number of cycles per instruction is large
– in such situations graphical representation becomes difficult as there may be
thousands of states and even more arcs joining them
– a microprogram is specification : implementation is by ROM or PLA
• A microprogram is a sequence of microinstructions
– each microinstruction has eight fields (label + 7 functional)
• Label: used to control microcode sequencing
• ALU control: specify operation to be done by ALU
• SRC1: specify source for first ALU operand
• SRC2: specify source for second ALU operand
• Register control: specify read/write for register file
• Memory: specify read/write for memory
• PCWrite control: specify the writing of the PC
• Sequencing: specify choice of next microinstruction
 Microprogramming
• The Sequencing field value determines the execution order of the
microprogram
– value Seq : control passes to the sequentially next microinstruction
– value Fetch : branch to the first microinstruction to begin the next
MIPS instruction, i.e., the first microinstruction in the microprogram
– value Dispatch i : branch to a microinstruction based on control
input and a dispatch table entry (called dispatching):
• Dispatching is implemented by means of creating a table, called dispatch
table, whose entries are microinstruction labels and which is indexed by
the control input. There may be multiple dispatch tables – the value
Dispatch i in the sequencing field indicates that the i th dispatch table is
to be used
 Control Microprogram
• The microprogram corresponding to the FSM control shown
graphically earlier:
ALU Register PCWrite
Label control SRC1 SRC2 control Memory control Sequencing
Fetch Add PC 4 Read PC ALU Seq
Add PC Extshft Read Dispatch 1
Mem1 Add A Extend Dispatch 2
LW2 Read ALU Seq
Write MDR Fetch
SW2 Write ALU Fetch
Rformat1 Func code A B Seq
Write ALU Fetch
BEQ1 Subt A B ALUOut-cond Fetch
JUMP1 Jump address Fetch
Microprogram containing 10 microinstructions
Dispatch ROM 1
Op Opcode name Value
Dispatch ROM 2
000000 R-format Rformat1
Op Opcode name Value
000010 jmp JUMP1 100011 lw LW2
000100 beq BEQ1 101011 sw SW2
100011 lw Mem1
101011 sw Mem1 Dispatch Table 2
Dispatch Table 1
 Microcode: Trade-offs
• Specification advantages
– easy to design and write
– typically manufacturer designs architecture and microcode in parallel
• Implementation advantages
– easy to change since values are in memory (e.g., off-chip ROM)
– can emulate other architectures
– can make use of internal registers
• Implementation disadvantages
– control is implemented nowadays on same chip as processor so the advantage of an off-chip ROM
does not exist
– ROM is no longer faster than on-board cache
– there is little need to change the microcode as general-purpose computers are used far more
nowadays than computers designed for specific applications
 Multi-cycle Example
• Datapath
– Will walk and $1, $2, $3 through datapath
• Look at control FSM
– Will walk and $1, $2, $3 through FSM
• Will skip
– Repeat for lw, sw, beq taken, beq n-t, j
 Multicycle Control Step (1):
Fetch
IR = Memory[PC];
PC = PC + 4;
1
IRWrite

I 28 32
1 R
Instruction I
5
jmpaddr
I[25:0] <<2 CONCAT
PCWr* rs rt rd
0
IorD 0 32 5 5
0
MUX
1 RegDst
0
2
M

PC
5 X ALUSrcA 010
Operation
1U
0
X

MemWrite RN1 RN2 WN 3

0M 0M
U
1X
ADDR M Registers U PCSource
D A 1X Zero
Memory
RD R
1M
U
0X
WD
RD1
ALU 0
ALU
OUT
WD RD2 B 0
MemRead MemtoReg 4 1M
U

X RegWrite
2X
3
1 0 E
16 X 32
ALUSrcB
immediate
T
N
<<2 1
D
 Multicycle Control Step (2):
Instruction Decode & Register Fetch
A = Reg[IR[25-21]]; (A = Reg[rs])
B = Reg[IR[20-15]]; (B = Reg[rt])
ALUOut = (PC + sign-extend(IR[15-0]) << 2);
0IRWrite

I
0 Instruction I jmpaddr 28 32
R 5 I[25:0] <<2 CONCAT
PCWr* rs rt rd
X 0 1 RegDst 0 2
IorD 0 32 5 5 MUX
5 X ALUSrcA 010 1U
M

X
PC Operation 0
MemWrite RN1 RN2 WN 3
0M 0M
U
1X
ADDR M Registers U PCSource
Zero
Memory
RD
D
R
1M
U WD
RD1 A 1X
ALU X
0X ALU
OUT
WD RD2 B 0
MemRead MemtoReg 4 1M
X
U
2X
3
0 RegWrite
0 E
X ALUSrcB
immediate 16
T
32
<<2 3
N
D
 Multicycle Control Step (3):
ALU Instruction (R-Type)
ALUOut = A op B;
0
IRWrite

I 28 32
0 R
Instruction I
5
jmpaddr
I[25:0] <<2 CONCAT
PCWr* rs rt rd
X 0 1 RegDst
1
2
IorD 0 32 5 5 MUX
5 X ALUSrcA ??? 1U
M

X
PC Operation 0
MemWrite RN1 RN2 WN 3
0M 0M
U
1X
ADDR M Registers U PCSource
1X Zero
D A
Memory
RD R
1M
U
0X
WD
RD1
ALU X
ALU
OUT
WD RD2 B 0
MemRead MemtoReg 4 1M
U
X RegWrite
2X
3
0 0 E
16 X 32
ALUSrcB
immediate
T
N
<<2 0
D
 Multicycle Control Step (4):
ALU Instruction (R-Type)
Reg[IR[15:11]] = ALUOut; (Reg[Rd] =
ALUOut) 0 IRWrite

I Instruction I jmpaddr 28 32
0
PCWr*
R
rs rt
5
rd
I[25:0] <<2 CONCAT

X 32 0 1 RegDst
X
2
M
0
5 5 MUX
IorD
1 XXX
1U
5 ALUSrcA X
PC Operation 0
MemWrite RN1 RN2 WN 3
0M 0M
U ADDR M Registers U PCSource
1X Zero
Memory D 0 M RD1 A 1X
RD R 1
U
X
WD ALU
ALU
X
OUT
WD RD2 B 0
MemRead MemtoReg 4 1M
U
2X
1 RegWrite 3

0 1 E
ALUSrcB
immediate 16 X 32
T
N
<<2 X
D
Multi-cycle IF MemRead
ALUSrcA=0
IorD = 0
IRWrite
ID
ALUSrcA = 0

Example
ALUSrcB = 11
Start ALUSrcB = 01
ALUOp = 00 ALUOp = 00
PCWrite
PCSrc = 00

(and) LW | SW
RRR
ALUSrcA = 1
BEQ
J

ALUSrcA = 1 ALUSrcA = 1 ALUSrcB = 00

EX ALUSrcB = 10 ALUSrcB = 00 ALUOp = 01
PCWrite
PCSource = 10
ALUOp = 00 ALUOp = 10 PCWriteCond
PCSource = 01

LW SW

WB
MEM MemRead MemWrite
RegDst = 1
RegWrite
IorD = 1 IorD = 1
MemtoReg = 0

RegDst = 0
WB RegWrite
MemtoReg = 1
Multi-cycle Example (and)
 Multicycle Control Step (3):
Memory Reference Instructions
ALUOut = A + sign-extend(IR[15-0]);
0
IRWrite

I Instruction I jmpaddr 28 32
0
PCWr*
R
rs rt
5
rd
I[25:0] <<2 CONCAT

X 32
0 1 RegDst
1
2
0 5 5 MUX M
IorD
PC
5 X ALUSrcA 010
Operation
1U
0
X

MemWrite RN1 RN2 WN 3

0M 0M
U
1X
ADDR M Registers U PCSource
D 1M RD1 A 1X Zero
Memory
RD R U
0X
WD ALU
ALU
X
OUT
WD RD2 B 0
MemRead MemtoReg 4 1M
U

X
2X
3
RegWrite
0 0 E
X ALUSrcB
immediate 16 32
T
N
<<2 2
D
 Multicycle Control Step (4):
Memory Access - Read (lw)
MDR = Memory[ALUOut];
IRWrite 0

I 28 32
0 R
Instruction I
5
jmpaddr
I[25:0] <<2 CONCAT
PCWr* rs rt rd
1 0 1 RegDst
X
2
IorD 0 32 5 5 MUX
5 X ALUSrcA XXX 1U
M

X
PC Operation 0
MemWrite RN1 RN2 WN 3
0M 0M
U
1X
ADDR M Registers U PCSource
D A 1X Zero
RD1
X
1M
Memory WD ALU
RD R U
0X ALU
OUT
WD RD2 B 0
MemRead MemtoReg 4 1M
U
X RegWrite
2X
3
1 0 E
16 X 32
ALUSrcB
immediate
T
N
<<2 X
D
 Multicycle Execution Steps (5)
Memory Read Completion (lw)
Reg[IR[20-16]] = MDR;
IRWrite 0

I 28 32
0 R
Instruction I
5
jmpaddr
I[25:0] <<2 CONCAT
PCWr* rs rt rd
X 0 1 RegDst
X 2
IorD 0 32 5 5 MUX
5 0 ALUSrcA XXX 1U
M

X
PC Operation 0
MemWrite RN1 RN2 WN 3
0M 0M
U ADDR M U PCSource
1X Registers Zero
D A
X
0 RD1 1X
Memory M
U WD ALU
RD R 1 X ALU
OUT
WD RD2 B 0
MemRead MemtoReg 4 1M
U

0 RegWrite
2X
3
0
16
1 E
X 32
ALUSrcB
X
immediate
T <<2
N
D
Multi-cycle IF MemRead
ALUSrcA=0
IorD = 0
IRWrite
ID
ALUSrcA = 0

Example
ALUSrcB = 11
Start ALUSrcB = 01
ALUOp = 00 ALUOp = 00
PCWrite
PCSrc = 00

(lw) LW | SW
RRR
ALUSrcA = 1
BEQ
J

ALUSrcA = 1 ALUSrcA = 1 ALUSrcB = 00

EX ALUSrcB = 10 ALUSrcB = 00 ALUOp = 01
PCWrite
PCSource = 10
ALUOp = 00 ALUOp = 10 PCWriteCond
PCSource = 01

LW SW

WB
MEM MemRead MemWrite
RegDst = 1
RegWrite
IorD = 1 IorD = 1
MemtoReg = 0

RegDst = 0
WB RegWrite
MemtoReg = 1
Multi-cycle Example (lw)
 Multicycle Execution Steps (4)
Memory Access - Write (sw)
Memory[ALUOut] = B;
IRWrite 0

I Instruction I jmpaddr 28 32
0
PCWr*
R
rs rt
5
rd
I[25:0] <<2 CONCAT

1 32
0 1 RegDst
X
2
1 5 5 MUX M
IorD
5 X ALUSrcA XXX 1U
X
PC Operation 0
MemWrite RN1 RN2 WN 3
0M 0M
U
1X
ADDR M Registers U PCSource
1X Zero
D 1M RD1 A
Memory
RD R U
0X
WD ALU
ALU
X
OUT
WD RD2 B 0
MemRead MemtoReg 4 1M
U

X RegWrite
2X
3
0 0 E
16 X 32
ALUSrcB
immediate
T
N
<<2 X
D
Multi-cycle IF MemRead
ALUSrcA=0
IorD = 0
IRWrite
ID
ALUSrcA = 0

Example
ALUSrcB = 11
Start ALUSrcB = 01
ALUOp = 00 ALUOp = 00
PCWrite
PCSrc = 00

(sw) LW | SW
RRR
ALUSrcA = 1
BEQ
J

ALUSrcA = 1 ALUSrcA = 1 ALUSrcB = 00

EX ALUSrcB = 10 ALUSrcB = 00 ALUOp = 01
PCWrite
PCSource = 10
ALUOp = 00 ALUOp = 10 PCWriteCond
PCSource = 01

LW SW

WB
MEM MemRead MemWrite
RegDst = 1
RegWrite
IorD = 1 IorD = 1
MemtoReg = 0

RegDst = 0
WB RegWrite
MemtoReg = 1
Multi-cycle Example (sw)
Multi-cycle IF MemRead
ALUSrcA=0
IorD = 0
IRWrite
ID
ALUSrcA = 0

Example
ALUSrcB = 11
Start ALUSrcB = 01
ALUOp = 00 ALUOp = 00
PCWrite
PCSrc = 00

(beq T) LW | SW
RRR
ALUSrcA = 1
BEQ
J

ALUSrcA = 1 ALUSrcA = 1 ALUSrcB = 00

EX ALUSrcB = 10 ALUSrcB = 00 ALUOp = 01
PCWrite
PCSource = 10
ALUOp = 00 ALUOp = 10 PCWriteCond
PCSource = 01

LW SW

WB
MEM MemRead MemWrite
RegDst = 1
RegWrite
IorD = 1 IorD = 1
MemtoReg = 0

RegDst = 0
WB RegWrite
MemtoReg = 1
 Multicycle Control Step (3):
Branch Instructions
if (A == B) PC = ALUOut;
0
IRWrite

1 if I Instruction I jmpaddr 28 32
Zero=1 R 5 I[25:0] <<2 CONCAT
PCWr* rs rt rd
X 0 1 RegDst
1
2
IorD 0 32 5 5 MUX
5 X ALUSrcA 011 1U
M

X
PC Operation 0
MemWrite RN1 RN2 WN 3
0M 0M
U
1X
ADDR M Registers U PCSource
1X Zero
D A
Memory
RD R
1M
U
0X
WD
RD1
ALU 1
ALU
OUT
WD RD2 B 0
MemRead MemtoReg 4 1M
U
X RegWrite
2X
3
0 0 E
16 X 32
ALUSrcB
immediate
T
N
<<2 0
D
Multi-cycle Example (beq T)
Multi-cycle Example (beq NT)
 Multicycle Execution Step (3):
Jump Instruction
PC = PC[21-28] concat (IR[25-0] << 2);
0
IRWrite

I Instruction I jmpaddr 28 32
1
PCWr*
R
rs rt
5
rd
I[25:0] <<2 CONCAT

X 32
0 1 RegDst
X
2
0 5 5 MUX M
IorD
PC
5 X ALUSrcA XXX
Operation
1U
0
X

MemWrite RN1 RN2 WN 3

0M 0M
U
1X
ADDR M Registers U PCSource
1X Zero
Memory D 1M RD1 A
RD R U
0X
WD ALU
ALU
2
OUT
WD RD2 B 0
MemRead MemtoReg 4 1M
U

X
2X
3
RegWrite
0 0 E
X ALUSrcB
immediate 16 32
T
N
<<2 X
D
 IF MemRead
ALUSrcA=0
ID
Multi-cycleStart IorD = 0
IRWrite
ALUSrcB = 01
ALUOp = 00
ALUSrcA = 0
ALUSrcB = 11
ALUOp = 00

Example (j)
PCWrite
PCSrc = 00
LW | SW J
RRR BEQ
ALUSrcA = 1
ALUSrcA = 1 ALUSrcA = 1 ALUSrcB = 00
EX ALUSrcB = 10 ALUSrcB = 00 ALUOp = 01
PCWrite
PCSource = 10
ALUOp = 00 ALUOp = 10 PCWriteCond
PCSource = 01

LW SW

WB
MEM MemRead MemWrite
RegDst = 1
RegWrite
IorD = 1 IorD = 1
MemtoReg = 0

RegDst = 0
WB RegWrite
MemtoReg = 1
Multi-cycle Example (j)
 Summary
• Techniques described in this chapter to design datapaths and control
are at the core of all modern computer architecture
• Multicycle datapaths offer two great advantages over single-cycle
– functional units can be reused within a single instruction if they are
accessed in different cycles – reducing the need to replicate expensive
logic
– instructions with shorter execution paths can complete quicker by
consuming fewer cycles
• Modern computers, in fact, take the multicycle paradigm to a higher
level to achieve greater instruction throughput:
– pipelining (next topic) where multiple instructions execute simultaneously
by having cycles of different instructions overlap in the datapath
– the MIPS architecture was designed to be pipelined
 Conclusions
• MIPS ISA: Three instruction formats (R,I,J)
• One cycle per stage, Different stages per format
• One-Cycle Steps R-fmt lw sw beq j

1. Instruction Fetch
2. Instruction Decode
3. ALU ops / R-format Execution
4. R-format Completion/Mem Access
5. Memory Read Completion

Challenge: More involved control design

END