EE 271

Digital Circuits and

Systems
Faculty of Advanced Science and Technology
 Faculty of Advanced Science and Technology

LATCH/FLIP FLOP
(FF)

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Sequential switching circuits have the property that the output depends not only on
the present input but also on the past sequence of inputs. In effect, these circuits
must be able to “remember” something about the past history of the inputs in order
to produce the present output. Latches and flip-flops are commonly used memory
devices in sequential circuits. Basically, latches and flip-flops are memory devices
which can assume one of two stable output states and which have one or more
inputs that can cause the output state to change.

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Logic Gate
- Combinational circuits using NOT, AND, OR,
NAND, NOR, XOR, XNOR

Latch/Flip-Flop
• Sequential circuits
- RS, T, D, JK

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Preset & Clear

Preset (Pr)
- Pr active then Q =1 , do not care all the inputs
Clear (Clr hoặc Cl)
Clr active then Q = 0, do not care all the inputs
• Pr và Clr có thể tích cực mức 0 hay mức 1
• Reading more in 7.4.3 page 395, Brown 3rd Edition

Clock (Ck) signal

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Master - Slaver

When C is 1, the data was put into Master FF, and when C
is 0, the date is out of Slaver FF

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Mạch tạo sườn xuống

Trailing edge

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b. Leading edge

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• RS FF (Reset Set)
• TFF (Toggle)
• DFF (Data/Delay)
• JKFF (replace for RSFF and repair the X
status of RSFF: J  S, K  R)

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Phương trình logic của RSFF

FF: Q0 = 0

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Triger input

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TFF

T = Toggle (change status when T = 1)

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TFF

• Phương trình và dạng sóng minh họa

Q0 = 0

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 Giả thiết
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trạng thái
ban đầu
Q0=0

FF: Q0 = 0 When T is 1: Freq.

DevisionDivision 19
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If you prefer, instead, to get a divider other than the power of 2. How? If a divider to 5.
How many TFF we need 

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ASYNCHRONOUS COUNTERS

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SYNCHRONOUS COUNTERS

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D (“data” or “delay”)

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D (“data” or “delay”)

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Giả thiết: DFF có xung Ck tích

cực tại sườn xuống và trạng thái
DFF ban đầu Q0=0

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• Freq. Divider

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JKFF

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 GiảFaculty
thiết: JKFF có xung Ck tích
of Advanced Science and Technology

cực tại sườn xuống và trạng thái

ban đầu Q0=0
JKFF (tt)

Giữ
nguyên
trạng thái

Xóa Thiết lập Xóa

Đảo trạng
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JKFF others FF

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Bảng đầu vào kích của FF được dùng để thiết kế mạch

tuần tự (máy trạng thái hữu hạn FSM)

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RS FFJKFF

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Flip Flop RS  Flip Flop D

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Flip Flop D - Flip Flop RS

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Flip Flop D - Flip Flop JK

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