VIETNAM NATIONAL UNIVERSITY, HANOI

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University of Engineering & Technology

Digital Design
Lecture: Sequential Circuits and FSM

Xuan-Tu Tran, PhD

Vietnam National University, Hanoi
Smart Integrated Systems (SISLAB) Research Group
Email: tutx@vnu.edu.vn

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Outline

⚫ Introduction to sequential circuits

⚫ Delay in gate networks
⚫ Flip-Flops (RS, JK, D)
⚫ Counters (Binary, BCD, Johnson)
⚫ Shift registers (serial, parallel)
⚫ Finite State Machines (FSM)

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What are sequential circuits?

⚫ Combinational circuits
⚫ The outputs are functions only of the present inputs

⚫ Sequential circuits
⚫ The outputs can be made functions of not only the present inputs, but also
some set of past inputs as well.
⚫ Sequential circuits have memory because one or more of the outputs are
“fed back” to serve as inputs the network.

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Delay in gate networks

⚫ Propagation delay per gate (Thời gian trễ lan truyền):

X
X Y
Y

Td1 Td2

Td 1 + Td 2
Td =
2
TTL logic family: Td varies from 1 to 15 ns
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Delay in gate networks (cont’d)

Ideal NAND gate has

⚫ Propagation delay in a NAND gate zero propagation delay

(a) non-ideal NAND gate

(b) Ideal NAND gate with delay

Timing diagram
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Delay in gate networks (cont’d)

⚫ Generation of a “glitch” in a combinational circuit.

Timing diagrams assuming

that B and C are both high
throughout.

“Glitch” dues to the physical

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delays in a network 6

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Delay in gate networks (cont’d)

⚫ Adding the consensus (đồng

tâm) to the equation

The glitch will vanish because

BC = 1 throughout the various
transitions on A and A-bar

Note: Remove the consensus may cause undesired behavior

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Flip-Flop (FF)

⚫ Is a memory element who has two stable states (‘0’ and ‘1’)

⚫ When it goes to a stable state, it will stay there until a control signal active.

⚫ The next state depends on both its input signals and its current state.

⚫ Built from basic logic gates

⚫ RS, JK, D

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Simple SR Flip-Flop

⚫ Simple SR Flip-Flop (inputs active at high level)

Sn Rn Qn+1 Mode
S Q
0 0 Qn Remain
R Q
1 0 1 Set

0 1 0 Reset
Qn +1 = RnQn + S n 1 1 Not allowed Not allowed

S S
Q

Q
R Q
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Simple SR Flip-Flop (cont’d)

⚫ Simple SR Flip-Flop (inputs active at low level)

Sn Rn Qn+1
S(L) Q
L L Not allowed
R(L) Q L H H
H L L
H H Qn

S(L) S(L)
Q

R(L)

Q
R(L)
Q

Note: Status of FF will not be stable if its inputs impacted by interferences

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Clocked SR Flip-Flop (cont’d)

⚫ SR Flip-Flop with clock input

⚫ Use a clock signal to enable the
inputs → the circuit will be more
stable.

S Q

Clk
tn tn+1
R Q
Sn Rn Qn+1
0 0 Qn
S Q
1 0 1
Clk
0 1 0
R Q
1 1 Not allowed

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Clocked SR Flip-Flop (cont’d)

⚫ SR Flip-Flop with clock input

tn tn+1 Clk
Sn Rn Qn+1
0 0 Qn
1 0 1 Q
0 1 0
Timing diagram
1 1 Not allowed
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Master-Slave SR Flip-Flop

⚫ Latch-mode Flip-Flop
When G is asserted → the output will
follow the changes in S and R
lines (If the S and R change more
than once → the output Q will change
more than once)
!!! undesirable characteristic

⚫ Master-Slave SR Flip-Flop

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Master-Slave SR Flip-Flop

⚫ Master-Slave Flip-Flop

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JK Flip-Flop

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Counters (Binary, BCD, Johnson)

⚫ In the text book !!!

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Shift registers (serial, parallel)

⚫ In the text book !!!

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Finite State Machines

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Models for clocked sequential circuits

State machine

Model of a combinational circuit

with feedback

Q = f ( q, X )
Z = h( q, X )
Mealy model for sequential circuits

Q = f ( q, X )
Moore model for sequential circuits Z = h( q )
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Finite State Machines (FSMs)

⚫ Any Circuit with Memory Is a Finite State Machine

⚫ Even computers can be viewed as huge FSMs

⚫ Design of FSMs Involves

⚫ Defining states
⚫ Defining transitions between states
⚫ Optimization / minimization

⚫ Above Approach Is Practical for Small FSMs Only

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Moore FSM

⚫ Output Is a Function of a Present State Only

Inputs Next State

function
Next State Present State
clock Present State
reset Register

Output Outputs
function
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Mealy FSM
⚫ Output Is a Function of a Present State and Inputs

Inputs Next State

function
Next State Present State
clock Present State
reset Register

Output Outputs
function
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Moore Machine

transition
condition 1

state 1 / state 2 /
output 1 output 2
transition
condition 2

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Mealy Machine

transition condition 1 /
output 1

state 1 state 2
transition condition 2 /
output 2

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Moore vs. Mealy FSM (1)

⚫ Moore and Mealy FSMs Can Be Functionally Equivalent

⚫ Equivalent Mealy FSM can be derived from Moore FSM and vice versa

⚫ Mealy FSM Has Richer Description and Usually Requires Smaller

Number of States
⚫ Smaller circuit area

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Moore vs. Mealy FSM (2)

⚫ Mealy FSM Computes Outputs as soon as Inputs Change

⚫ Mealy FSM responds one clock cycle sooner than equivalent Moore FSM

⚫ Moore FSM Has No Combinational Path Between Inputs and

Outputs
⚫ Moore FSM is more likely to have a shorter critical path

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Moore FSM - Example 1

⚫ Moore FSM that Recognizes Sequence “10”

0 1
0
1
S0 / 0 S1 / 0 1 S2 / 1

reset
0
S0: No S1: “1” S2: “10”
Meaning elements observed observed
of states: of the
sequence
observed
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Mealy FSM - Example 1

⚫ Mealy FSM that Recognizes Sequence “10”

0/0 1/0 1/0

S0 S1

reset 0/1
S0: No S1: “1”
Meaning elements observed
of states: of the
sequence
observed
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Moore & Mealy FSMs – Example 1

clock
0 1 0 0 0
input

S0 S1 S2 S0 S0
Moore
S0 S1 S0 S0 S0
Mealy

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Finite State Machine (FSM)

FSM for a sequence detector that detects the sequence 101

Home work: Students draw the timing diagram for their given input data
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