VIETNAM NATIONAL UNIVERSITY HANOI (VNU)

VNU INFORMATION TECHNOLOGY INSTITUTE (VNU-ITI)

Digital Design
Common Logic Families

Xuan-Tu Tran, PhD

VNU Laboratory for Smart Integrated Systems (SISLAB)
Email: tutx@vnu.edu.vn
www.uet.vnu.edu.vn/~tutx

Outline

❑ Common features of logic families

❑ Resistor-Transistor-Logic (RTL) family

❑ Diode-Transistor-Logic (DTL) family

❑ Transistor-Transistor-Logic (TTL) family

❑ MOSFET transistors

❑ CMOS logic family

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 Common features of logic families

❑Having two voltage levels: VH and VL (logic 0 & 1, or L & H)

❑Being supplied by a reference voltage
❑Basic parameters:
– Output impedance (Trở kháng ra): varies depending on the status of the output (H or L).
– Fan out (Hệ số mắc tải): the capability of the output in driving the inputs of the followed
circuits (the number of inputs that it can drive).
– Fan in (Hệ số hợp lối vào): the capability of the input in merging the output of the
preceded circuits.
– Power supply: type of circuits; use filter capacitors (0,1µF) to avoid suddenly voltage
changing.

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Common features of logic families

– Propagation delay per gate (Thời gian trễ lan truyền):

X
X Y
Y

Td1 Td2

Td 1 + Td 2
Td =
2

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 Common features of logic families

– Power dissipated per gate (Công suất tiêu thụ đối với một gate)
▪ Depending on the number AND/OR the value of resistors in circuits, working status of transistors
(saturated status).

▪ For example, TTL 74XX: 10mW/gate; TTL 74LXX: 1mW/gate; TTL 74HXX: 22mW/gate.

▪ p-MOS and n-MOS dissipate fewer than other logic families.

– Noise immunity level (Mức độ chống tạp âm):

▪ highest amplitude of noise can be entered to the circuit without any change at the output of the
circuit.

– Maximum clock rate (Tần số xung nhịp cực đại)

▪ In invert proportion to propagation delay (of the gated used in constructing the circuit).

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RTL: Resistor-Transistor-Logic

❑ Resistors and transistors are used in constructing logic gates

❑ Power supply: VCC = +3.6 Volt

❑ Logic voltage levels:

– L or logic ‘0’: 0 Volt

– H or logic ‘1’: > 1.5 volt

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 RTL: Resistor-Transistor-Logic

❑ NOT gate
VCC = +3.6 V

y=x 640 Ω R2
y
450 Ω
VC = VCC − I C R2 x
R1

When x = L ='0': I B = 0 → I C = 0
y = VC = VCC = H ='1'

When x = H ='1': I B → I C 
y = VC = VCC − I C R2 = L ='0'

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RTL: Resistor-Transistor-Logic

❑ NOR gate VCC = +3.6 V

640 Ω R2
y = x1 + x2
Y
T1 T2
R1
X1
450 Ω
VC = VCC − I C R2 X2
R1

When x1 = x2 = L : I B = 0 (T1 & T2 OFF) → I C = 0

y = VC = VCC = H

When x1 = H or x2 = H or x1 = x2 = H : I B → I C 
y = VC = VCC − I C R2 = L
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 RTL: Resistor-Transistor-Logic

❑ AND gate

y = x1 x2 VCC = +3.6 V

R2 R2 R2 = 640 Ω

y
y1 y2
T1 T2
R1 R1
x1 x2
T3 T4
450 Ω

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RTL: Resistor-Transistor-Logic

❑ AND gate

X1 Y1
T1
Y
T3,4
X2
T2
Y2

y = x1 + x2 = x1 x2

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 DTL: Diode-Transistor-Logic

❑ NOT gate
R2 VCC = +5 V
y=x
R1
R4
x
T1
y
Open-input → VB1 = H → T1 & T2 ON
T2
➔Y=L

x = H (> 2.2 V) → D1 OFF → VB1 = H R3

→ T1 & T2 ON, therefore y = L

x = L (= 0 V) → D1 ON → VB1 = L R1 = 2 kΩ
→ T1 & T2 OFF, therefore y = H R2 = 1.75 kΩ
R3 = 1 kΩ R4 = 6 kΩ
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DTL: Diode-Transistor-Logic

❑ NAND gate
R2 VCC = +5 V
y = x1 x2
R1
R4
x1
T1
x2 y

T2
2 parallel diodes used at the inputs
→ n-input NAND uses N parallel
R3
diodes at the inputs

Operating frequency (F) < 1 MHz

R1 = 2 kΩ
Discontinue ! R2 = 1.75 kΩ
R3 = 1 kΩ R4 = 6 kΩ
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 TTL: Transistor-Transistor-Logic

❑ Power supply: VCC = 5 V

❑ Logic voltage levels:
– V out H  2.4 Volt
– V out L = 0.2 V to 0.4 V
– V in L < 0.8 V
– V in H  2 V

❑ Notation
– SN 7400 (SN: Manufacturer: Texas Instrument; 74: 0°C to 70°C; 00: 2-input NAND gates; Td = 10
ns, f = 20 MHz)
– SN 5400 (54: -55°C to 125°C); SN 74L00 (L: Low power); SN 74H00 (H: High speed, Td = 6 ns, f =
50 MHz); SN 74LS00 (LS: low power, using Shottky diodes and transistors)

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TTL: Transistor-Transistor-Logic

❑ NOT gate VCC = +5 V

x = H (or open) → VB1, VB2 = H (T2 in R1 R2 R4

saturation) → VC2 low (T3 OFF),
VB4 = VE2 = IE2 . R3 = H (T4 ON) T3
T1
→y=L
x
T2
y
x = L → VB2 = L (T2 OFF) → VB3 =
VC2 = H (T3 ON), VB4 = VE2 = L T4
(T4 OFF) → y = H
R3
R1 = 4 kΩ 54/7404
R2 = 1.6 kΩ
R3 = 1 kΩ R4 = 130 Ω
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 TTL: Transistor-Transistor-Logic

❑ NAND gate
VCC = +5 V

How does it work ? R1 R2 R4

T3
T1
x1
T2
y
x2
T4

R3
R1 = 4 kΩ 54/7400
R2 = 1.6 kΩ
R3 = 1 kΩ R4 = 130 Ω
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TTL: Transistor-Transistor-Logic

❑ NOR gate
VCC = +5 V

How does it work ? R1 R1 R2 R4

T5
T1
T3 T4
x1

x2 y

T2 T6

R3
R1 = 4 kΩ
54/7402
R2 = 1.6 kΩ
R3 = 1 kΩ R4 = 130 Ω

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 FET: Field-Effect Transistor

❑ Basic
– Relies on an electric field to control the shape and hence the
conductivity of a channel of one type of charge carrier in
semiconductor material

– Terminals: Gate, Drain, and Source

– Different types of FET:

• JFET (Junction Field-Effect Transistor) uses a reverse biased p-n
junction to separate the gate from the body.

• MOSFET (Metal–Oxide–Semiconductor Field-Effect Transistor)

utilizes an insulator (typically SiO2) between the gate and the body.

• MESFET (Metal–Semiconductor Field-Effect Transistor) substitutes

the p-n junction of the JFET with a Schottky barrier; used in GaAs
and other III-V semiconductor materials

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MOSFET Transistors

2002: L=130nm
Key feature: 2003: L=90nm
transistor length L 2005: L=65nm
2007: L=45nm
2020: L=5nm
2022: L=3nm
2024: L=2nm ?

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 Transistor Switch Model

❑ We can view MOS transistors as electrically controlled switches

– Voltage at gate controls path from source to drain

• nFET or n transistor
– ON when gate = H

• pFET or p transistor
– ON when gate = L
g=0 g=1

d d d
nMOS g OFF
ON
s s s

d d d

pMOS g OFF
ON
s s s
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CMOS Logic Design

❑ Complementary transistor networks

– Pull-up: p transistors

– Pull-down: n transistors

VDD

VDD
Pullup
Network
(p-transistors)

Inputs Out In Out

Pulldown
Network
(n-transistors)
Gnd

Gnd Inverter

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 CMOS Inverter Operation

❑ Inverter operation

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CMOS NAND gate

❑ NAND gate

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 CMOS NOR gate

❑ NOR gate

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