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  • SV TB Archetecture

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    Rajesh Panda
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    The document discusses System Verilog testbenches. It explains that a testbench contains various components to generate input sequences, drive the Design Under Test (DUT), capture outputs, and compare outputs to expected results. It provides steps for developing a testbench, including creating a verification plan, defining the testbench architecture, and developing individual components like interfaces, clocking blocks, and modports.

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    SV Tb Archetecture

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    The document discusses System Verilog testbenches. It explains that a testbench contains various components to generate input sequences, drive the Design Under Test (DUT), capture outputs, and compare outputs to expected results. It provides steps for developing a testbench, including creating a verification plan, defining the testbench architecture, and developing individual components like interfaces, clocking blocks, and modports.

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    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    27 views12 pages

    SV TB Archetecture

    Uploaded by

    Rajesh Panda
    The document discusses System Verilog testbenches. It explains that a testbench contains various components to generate input sequences, drive the Design Under Test (DUT), capture outputs, and compare outputs to expected results. It provides steps for developing a testbench, including creating a verification plan, defining the testbench architecture, and developing individual components like interfaces, clocking blocks, and modports.

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    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
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    of 12

    1

    SYSTEM VERILOG
    TESTBENCH
    SYSTEM VERILOG ENVIRONMENT 2

     Verification environment is used for functional correctness of the Design Under Test by
    generating and driving a predefined(protocol oriented)input sequences ,capturing the
    design O/P and comparing wrt. Expected O/P
     Verification environment is formed by grouping several components performing specific
    task/operation
     In verification environment, separate classes are written to perform specific operation like
    stimulus generation, driving and monitoring etc and their naming is done according to their
    operation.
    ENVIRONMENT COMPONENTS
    3
    WITH DESCRIPTION
    STEPS TO DEVELOPE VERIFICATION 4

    ENVIRONMENT

     Creation of verification Plan


     Test-bench Architecture
     Component Development
    Verification Plan 5
     Prepare road-map for how to achieve the Goal(Document).
     Test plan includes
     Introduction
     Assumption
     List of Test-cases
     Features to be tested
     Approaches
     Resources
     Entry & Exit area
     Helps in understanding how the Verification process should be done
     Test plan also contains description of each component and their respective role in verification
    environment
    TESTBENCH ARCHITECTURE 6

    PACKAGE
    ENVIRONMENT

    GENERATOR

    REFERENC SCOREBOARD
    E MODEL

    WRITE WRITE READ READ BFM


    BFM MONITOR MONITOR

    DUV
    INTERFACE

    MAILBOX
    INTERFACE 7

     Static component
     Encapsulates communication between hardware blocks
     Bundle of Signals
     Reduce amount of code
     Promote reuse
     Synthesizable construct
     Can include always, initial, task, function, assertion and coverage too
    8
    EXAMPLE OF INTERFACE
    9
    MODPORT 10

     Permits customization of an interface for different blocks or modules


     Provides direction for individual module ports
     Specifies which signals in the interface are accessible to module
    Clocking Block(CB) 11

     Provides race-free operation


     Ensures “TB will drive the signals at the right time (clock edge)
     Setup and Hold time can be modelled

     Interface can have multiple clocking blocks


     Only one clock per CB
     It’s meant only for testbench
     Default clocking block
     Input skew-TB samples DUT output before the clock edge->1 clock cycle delay
     Output skew-TB drives DUT inputs at the clock edge-> No delay
    12

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