AURORA’S TECHNOLOGICAL AND RESEARCH INSTITUTE
(Accredited by NAAC with ‘A’ Grade) (Approved by AICTE and Affiliated to JNTU,
Hyderabad) Parvathapur Uppal, Hyderabad-500 098(2022-23)
ELECTRONICS AND COMMUNICATIONS ENGINEERING
COMPRESSOR BASED 8x8 A BIT VEDIC MULTIPLIER
USING REVERSIBLE LOGIC
PROJECT CO- INTERNAL GUIDE:
ORDINATOR : K.APARNA MR.S. RAJASHEKAR
Sr. Asst. Professor Sr. Associate
Professor
HEAD OF THE DEPARTMENT : DIRECTOR :
Mr. M. SHRAVAN KUMAR MR.SRIKANTH
REDDY JATLA
•STUDENT DETAILS :
•D.MANISHA --19841A0472
•A.JEEVAN KARTHIK -
19841A0498
CONTENTS
:
ABSTRACT
INTRODUCTION
EXISTING WORK
BLOCK DIAGRAM
LIMITATIONS
OBJECTIVES
PROPOSED SYSTEM
ADVANTAGES
HARDWARE REQUIREMENTS
SOFTWARE REQUIREMENTS
PROJECT ACTIVITY
DURATION
REFERENCES
ABSTRACT
:
This project specifies the modified version of binary Vedic multiplier using
Vedic sutras of ancient Vedic mathematics.
The modified binary Vedic multiplier is preferable has shown improvement in
the
terms of the time delay and also device utilization.
The outcomes of this multiplication technique is compared with existing
Vedic
`multiplier or booth multiplier techniques.
Multipliers are key components of DSP,
FIR filters etc....., and are generally the most
area consuming and power consuming units
in design
In early days vedic mathematics is based on
16 sutras. Based on these sutras, a
proposed system is developed which must be
efficient in terms of power, speed and size
INTRODUCTION as per growing technology.
: By using Vedic methods the mathematical
operations are fast and the processing speed
to perform the operations can be improved.
Based on carry, vedic multiplier can be
decided whether it is low power
consumption or high speed.
EXISTING
WORK :
A binary multiplier [3] can be used in digital electronics as a
electronic circuit, such as in computers to find the product of two
binary numbers.
Carbon-copy of normal multiplication technique is used by
binary multiplier, the multiplicand is multiplied with each bit of
the multiplier beginning from the least significant bit.
Two half adder (HA) modules can be used in order to implement a
2-bit binary multiplier.
Among these techniques many imply computing a set of partial
products, and then summing the generated partial products
together
EXISTING
SYSTEM
BLOCK
DIAGRAM
:
LIMITATIONS OF EXISTING
WORK :
Effective partial products structure needs to be
implemented
Other sutras on vedic would effectively reduce
multiplication
Higher bits would result in complex designs
OBJECTIVES
:
• Improved carry select adder design for low power application
• Efficient 2-bit multiplier with effective gates utilization.
• X-NOR, MUX models utilized for Effective Full adder and
Multiplier.
PROPOSED
SYSTEM :
Compressor is just nothing but all the half adders, full adders all
together placed in a single block diagram.
Vedic multiplier is based upon 16 sutras in vedic mathematics .
The "Urdhva Tiryakbhyam" sutra is used in vedic multiplier.
Conceptual meaning of this sutra is "perpendicularly and diagonally".
The working of the algorithm is with the calculation of partial
products. Simultaneous addition of partial products are carried out
with this
Reversible logic gates are circuit that have one - to - one mapping
between vectors of input and output. By using this logic full adders
or half adders are replaced by freyman gate, fredkin gate etc .
Combining the vedic sutra- "Urdhva Tiryabhyam" and efficient
compressors, a robust area and power efficient multiplier architecture
have been achieved
Urdhva Tiryagbhyam algorithm for binary
multiplication :
ADVANTAGES
:
Low power consumptions.
Efficient area based on carry select
adder
Reliable performance
Effective adder circuit for UT
multiplication
HARDWARE
REQUIREMENTS
:
Any PC with I(3,5,7)
processors
8 GB RAM
512 HDD
SOFTWARE
REQUIREMENTS
:
Model
sim
Xilinx
This Photo by Unknown author is licensed under C C BY.
PROJECT ACTIVITY
DURATION :
TOTAL DURATION : ONE MONTH
WEEK 1 : Problem identification, literature
survey
WEEK 2: Working on software model sim and
xilinx
WEEK 3: Writing code for vedic multiplier
WEEK 4: Execution of project
REFERENCES
:
S. Akhter, “VHDL implementation of fast NxN multiplier based on Vedic
mathematics,” in Proc. 18th European Conference on Circuit Theory and
Design, 2007, pp. 472-475
S. Nagaraj, Dr.G.M. Sreerama Reddy and Dr.S. Aruna Mastani; A
Comparative Study on Different Multipliers-SurveyJournal of Advanced
Research in Dynamical and Control Systems14739-7522018Institute of
Advanced Scientific Research.
M.Pushpa, S. Nagaraj, Design and Analysis of 8-bit Array, Carry Save
Array, Braun,Wallace Tree and Vedic Multipliers, IEEE Sponsored
International Conference On New Trends In Engineering &
Technology( ICNTET 2018).
THANK
YOU!!
