12 Processos e Wait

RASSP E&F
SCRA GT UVA Raytheon

UCinc EIT ADL
Behavioral VHDL
RASSP Education & Facilitation
Module 12
Version 2.01
Copyright  1995-1998 RASSP E&F
All rights reserved. This information is copyrighted by the RASSP E&F Program
and may only be used for non-commercial educational purposes. Any other use of
this information without the express written permission of the RASSP E&F Program
is prohibited. All information contained herein may be duplicated for non-
commercial educational use provided this copyright notice is included. No warranty
of any kind is provided or implied, nor is any liability accepted regardless of use.
FEEDBACK:
The RASSP E&F Program welcomes and encourages any feedback that you may have including
any changes that you may make to improve or update the material. You can contact us at
feedback@rassp.scra.org or
http://rassp.scra.org/module-request/FEEDBACK/feedback-on-modules.html

Module Goals RASSP E&F
UCinc EIT ADL
 Increase comprehension of behavioral VHDL

constructs
 Expand knowledge of VHDL concepts and

syntax
 Assist in understanding the application of

behavioral VHDL to a real example

Introduction to Behavioral
Modeling in VHDL RASSP E&F
UCinc EIT ADL
 Abstraction levels of VHDL models

 Structural level
 Behavioral/structural mixed (i.e., data flow)
 Behavioral
 Behavioral Modeling
 Functional performance is the goal of behavioral
modeling
 Timing optionally included in the model
 Software engineering practices should be used to
develop behavioral models
 Structured design
 Iterative refinement
 Abstract data typing
 Loose coupling, strong cohesion
Example Behavioral VHDL
Model RASSP E&F
UCinc EIT ADL
USE TEXTIO.all, mypackage.all;

ENTITY module IS
PORT (X, Y: IN BIT; Z: out BIT_VECTOR(3 DOWNTO
0);
END module;
ARCHITECTURE behavior OF module IS
SIGNAL A, B: BIT_VECTOR(3 DOWNTO 0);
BEGIN
A(0) <= X AFTER 20 ns; A(1) <= Y AFTER 40 ns;
PROCESS (A)
VARIABLE P, Q: BIT_VECTOR(3 DOWNTO 0);
BEGIN
P := fft(A);
B <= P AFTER 10 ns;
END PROCESS;
Z <= B;
END behavior;
Module Outline RASSP E&F
UCinc EIT ADL
 Introduction
 Behavioral Modeling
 Processes
 Sequential statements
 Subprograms
 Packages
 Problems to avoid
 Examples
 Summary

VHDL Processes RASSP E&F
UCinc EIT ADL
 A VHDL process statement is used for all

behavioral descriptions
 Example simple VHDL process:
ARCHITECTURE behavioral OF clock_component IS
BEGIN
PROCESS
VARIABLE periodic: BIT := ‘1’;
BEGIN
IF en = ‘1’ THEN
periodic := not periodic;
END IF;
ck <= periodic;
WAIT FOR 1 us;
END PROCESS;
END behavioral;
Process Syntax RASSP E&F
UCinc EIT ADL
[ process_label : ] PROCESS
[( sensitivity_list )]
NO
process_declarations SIGNAL
DECLARATIONS!
BEGIN
process_statements
END PROCESS [ process_label ] ;

VHDL Sequential Statements RASSP E&F
UCinc EIT ADL
 Assignments executed sequentially in processes

 Sequential statements
 {Signal, variable} assignments
 Flow control
 IF <condition> THEN <statements> [ELSIF <statements] [ELSE
<statements>] END IF;
 FOR <range> LOOP <statements> END LOOP;
 WHILE <condition> LOOP <statements> END LOOP;
 CASE <condition> IS WHEN <value> => <statements>
{WHEN <value> => <statements>}

[WHEN others => <statements>]
END CASE;
 WAIT [ON <signal>] [UNTIL <expression>] [FOR <time>] ;
 ASSERT <condition> [REPORT <string>] [SEVERITY <level>] ;

The Wait Statement RASSP E&F
UCinc EIT ADL
 The wait statement causes the suspension of a process

statement or a procedure
 wait [sensitivity_clause] [condition_clause] [timeout_clause ] ;
 sensitivity_clause ::= ON signal_name { , signal_name }
WAIT ON clock;
 condition_clause ::= UNTIL boolean_expression
WAIT UNTIL clock = ‘1’;
 timeout_clause ::= FOR time_expression
WAIT FOR 150 ns;

Equivalent Processes RASSP E&F
UCinc EIT ADL
 “Sensitivity List” vs “wait on”
Summation: Summation: PROCESS

PROCESS( A, B, Cin) BEGIN
BEGIN
Sum <= A XOR B XOR Cin;
= Sum <= A XOR B XOR Cin;
WAIT ON A, B, Cin;
END PROCESS Summation; END PROCESS Summation;
if you put a sensitivity list in a process,

you can’t have a wait statement!
if you put a wait statement in a process,

you can’t have a sensitivity list!

“wait until” and “wait for” RASSP E&F
UCinc EIT ADL
 What do these do?
Summation: PROCESS
BEGIN
WAIT UNTIL A = ‘1’;
END PROCESS Summation;
Summation: PROCESS
BEGIN
WAIT FOR 100 ns;
END PROCESS Summation;

Mix and Match RASSP E&F
UCinc EIT ADL
 Within an architecture we have two signals and

the following process
DoSomething: PROCESS
BEGIN
WAIT ON TheirSignal;
OurSignal <= ‘1’;

WAIT FOR 10 ns;

WAIT UNTIL (TheirSignal = ‘1’);
END PROCESS DoSomething;


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RASSP E&F

SCRA GT UVA Raytheon

Copyright  1995-1998 RASSP E&F

 Increase comprehension of behavioral VHDL

 Expand knowledge of VHDL concepts and

 Assist in understanding the application of

Copyright  1995-1998 RASSP E&F

 Abstraction levels of VHDL models

USE TEXTIO.all, mypackage.all;

Copyright  1995-1998 RASSP E&F

 A VHDL process statement is used for all

END PROCESS [ process_label ] ;

Copyright  1995-1998 RASSP E&F

 Assignments executed sequentially in processes

{WHEN <value> => <statements>}

Copyright  1995-1998 RASSP E&F

 The wait statement causes the suspension of a process

Copyright  1995-1998 RASSP E&F

 “Sensitivity List” vs “wait on”

Summation: Summation: PROCESS

if you put a sensitivity list in a process,

if you put a wait statement in a process,

Copyright  1995-1998 RASSP E&F

 What do these do?

Copyright  1995-1998 RASSP E&F

 Within an architecture we have two signals and

OurSignal <= ‘1’;

OurSignal <= ‘0’;

OurSignal <= ‘1’;

END PROCESS DoSomething;

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