7 Modelo Comportamental

RASSP E&F
SCRA GT UVA Raytheon

UCinc EIT ADL
Behavioral VHDL
RASSP Education & Facilitation
Module 12
Version 2.01
Copyright  1995-1998 RASSP E&F
All rights reserved. This information is copyrighted by the RASSP E&F Program
and may only be used for non-commercial educational purposes. Any other use of
this information without the express written permission of the RASSP E&F Program
is prohibited. All information contained herein may be duplicated for non-
commercial educational use provided this copyright notice is included. No warranty
of any kind is provided or implied, nor is any liability accepted regardless of use.
FEEDBACK:
The RASSP E&F Program welcomes and encourages any feedback that you may have including
any changes that you may make to improve or update the material. You can contact us at
feedback@rassp.scra.org or
http://rassp.scra.org/module-request/FEEDBACK/feedback-on-modules.html

Module Goals RASSP E&F
UCinc EIT ADL
 Increase comprehension of behavioral VHDL

constructs
 Expand knowledge of VHDL concepts and

syntax
 Assist in understanding the application of

behavioral VHDL to a real example

Introduction to Behavioral
Modeling in VHDL RASSP E&F
UCinc EIT ADL
 Abstraction levels of VHDL models

 Structural level
 Behavioral/structural mixed (i.e., data flow)
 Behavioral
 Behavioral Modeling
 Functional performance is the goal of behavioral
modeling
 Timing optionally included in the model
 Software engineering practices should be used to
develop behavioral models
 Structured design
 Iterative refinement
 Abstract data typing
 Loose coupling, strong cohesion
Example Behavioral VHDL
Model RASSP E&F
UCinc EIT ADL
USE TEXTIO.all, mypackage.all;

ENTITY module IS
PORT (X, Y: IN BIT; Z: out BIT_VECTOR(3 DOWNTO
0);
END module;
ARCHITECTURE behavior OF module IS
SIGNAL A, B: BIT_VECTOR(3 DOWNTO 0);
BEGIN
A(0) <= X AFTER 20 ns; A(1) <= Y AFTER 40 ns;
PROCESS (A)
VARIABLE P, Q: BIT_VECTOR(3 DOWNTO 0);
BEGIN
P := fft(A);
B <= P AFTER 10 ns;
END PROCESS;
Z <= B;
END behavior;
Module Outline RASSP E&F
UCinc EIT ADL
 Introduction
 Behavioral Modeling
 Processes
 Sequential statements
 Subprograms
 Packages
 Problems to avoid
 Examples
 Summary

VHDL Processes RASSP E&F
UCinc EIT ADL
 A VHDL process statement is used for all

behavioral descriptions
 Example simple VHDL process:
ARCHITECTURE behavioral OF clock_component IS
BEGIN
PROCESS
VARIABLE periodic: BIT := ‘1’;
BEGIN
IF en = ‘1’ THEN
periodic := not periodic;
END IF;
ck <= periodic;
WAIT FOR 1 us;
END PROCESS;
END behavioral;
Process Syntax RASSP E&F
UCinc EIT ADL
[ process_label : ] PROCESS
[( sensitivity_list )]
NO
process_declarations SIGNAL
DECLARATIONS!
BEGIN
process_statements
END PROCESS [ process_label ] ;

Let’s Write a VHDL Model ... RASSP E&F
UCinc EIT ADL
A ENTITY full_adder IS
Sum PORT ( A, B, Cin : IN BIT;
B Sum, Cout : OUT BIT );
Cout END full_adder;
Cin
Can we build the Full Adder’s architecture using these gates?

Full Adder Architecture RASSP E&F
UCinc EIT ADL
A B Cin Sum Cout

0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1 for Cout (I.e. Carry Out):
1 1 1 1 1
Cin (I.e. Carry In)
AB 0 1
00 0 0
01 0 1
11 1 1
10 0 1
for Sum:
Cin (I.e. Carry In):
AB 0 1
00 0 1
01 1 0
11 0 1
10 1 0

Two Full Adder Processes RASSP E&F
UCinc EIT ADL
Summation:
PROCESS( A, B, Cin)
BEGIN
Sum <= A XOR B XOR Cin;
END PROCESS Summation;
A
Sum
B
Cout
Cin
Carry:
PROCESS( A, B, Cin)
BEGIN
Cout <= (A AND B) OR
(A AND Cin) OR
(B AND Cin);
END PROCESS Carry;
Complete Architecture RASSP E&F
UCinc EIT ADL
ARCHITECTURE example OF full_adder IS

-- Nothing needed in declarative block...
BEGIN
Summation: PROCESS( A, B, Cin)

BEGIN
Sum <= A XOR B XOR Cin;
END PROCESS Summation;
Carry: PROCESS( A, B, Cin)

BEGIN
Cout <= (A AND B) OR
(A AND Cin) OR
(B AND Cin);
END PROCESS Carry;
END example;

Alternate Carry Process RASSP E&F
UCinc EIT ADL
Carry: PROCESS( A, B, Cin)

BEGIN
IF ( A = ‘1’ AND B = ‘1’ ) THEN
Cout <= ‘1’;
ELSIF ( A = ‘1’ AND Cin = ‘1’ ) THEN
Cout < = ‘1’;
ELSIF ( B = ‘1’ AND Cin = ‘1’ ) THEN
Cout <= ‘1’;
ELSE
Cout <= ‘0’;
END IF;
END PROCESS Carry;

VHDL Sequential Statements RASSP E&F
UCinc EIT ADL
 Assignments executed sequentially in processes

 Sequential statements
 {Signal, variable} assignments
 Flow control
 IF <condition> THEN <statements> [ELSIF <statements] [ELSE
<statements>] END IF;
 FOR <range> LOOP <statements> END LOOP;
 WHILE <condition> LOOP <statements> END LOOP;
 CASE <condition> IS WHEN <value> => <statements>
{WHEN <value> => <statements>}

[WHEN others => <statements>]
END CASE;
 WAIT [ON <signal>] [UNTIL <expression>] [FOR <time>] ;
 ASSERT <condition> [REPORT <string>] [SEVERITY <level>] ;

References RASSP E&F
UCinc EIT ADL
[Ashenden], Peter Ashenden, “The VHDL Cookbook,” Available via ftp from thor.ece.uc.edu.
[IEEE93], “The VHDL Language Reference Manual,” IEEE Standard 1076-93, 1993.
[Jain91], Ravi Jain, The Art of Computer Systems Performance Analysis, John Wiley & Sons, 1991.
[Navabi93], Zain Navabi, VHDL: Analysis and Modeling of Digital Systems McGraw Hill, 1993.
[Mohanty95], Sidhatha Mohanty, V. Krishnaswamy, P. Wilsey, “Systems Modeling, Performance

Analysis, and Evolutionary Prototyping with Hardware Description Languages,” Proceedings of
the 1995 Multiconference on Simulation, pp 312-318.

7 Modelo Comportamental

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RASSP E&F

SCRA GT UVA Raytheon

Copyright  1995-1998 RASSP E&F

 Increase comprehension of behavioral VHDL

 Expand knowledge of VHDL concepts and

 Assist in understanding the application of

Copyright  1995-1998 RASSP E&F

 Abstraction levels of VHDL models

USE TEXTIO.all, mypackage.all;

Copyright  1995-1998 RASSP E&F

 A VHDL process statement is used for all

END PROCESS [ process_label ] ;

Copyright  1995-1998 RASSP E&F

Can we build the Full Adder’s architecture using these gates?

Copyright  1995-1998 RASSP E&F

A B Cin Sum Cout

Copyright  1995-1998 RASSP E&F

ARCHITECTURE example OF full_adder IS

Summation: PROCESS( A, B, Cin)

Carry: PROCESS( A, B, Cin)

Copyright  1995-1998 RASSP E&F

Carry: PROCESS( A, B, Cin)

Copyright  1995-1998 RASSP E&F

 Assignments executed sequentially in processes

{WHEN <value> => <statements>}

Copyright  1995-1998 RASSP E&F

[Mohanty95], Sidhatha Mohanty, V. Krishnaswamy, P. Wilsey, “Systems Modeling, Performance

Copyright  1995-1998 RASSP E&F

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