Digital Systems Design Using VHDL Roth/John

Chapter 5

SM Charts and
Microprogramming

© 2018 Cengage Learning®. May not be scanned, copied or duplicated, or posted to a publicly
accessible website, in whole or in part.
5-1
Digital Systems Design Using VHDL Roth/John

Introduction
A state machine chart (SM chart) may be
used to describe the behavior of a state
machine. These charts are also called
algorithmic state machine charts (ASM
charts).
They are an alternative to using state graphs.
SM charts are often used to design control
units for digital systems.
Microprogramming is a technique for
implementing the SM chart.
© 2018 Cengage Learning®. May not be scanned, copied or duplicated, or posted to a publicly
accessible website, in whole or in part.
5-2
Digital Systems Design Using VHDL Roth/John

SM Charts
Resemble software flow charts.
Useful in hardware design.
Advantages over state graphs:
Easier to understand.
Conditions of a state graph are automatically
fulfilled in an SM chart.
Directly leads to a hardware realization.
May be converted into different equivalent
forms resulting in different implementations.

© 2018 Cengage Learning®. May not be scanned, copied or duplicated, or posted to a publicly
accessible website, in whole or in part.
5-3
Digital Systems Design Using VHDL Roth/John

SM Charts (continued)
Three components:
State box: a rectangular box; contains a state
name followed by a slash (/) and an optional output
list. After a state assignment has been made, a state
code may be placed outside the box at the top.
Decision box: a diamond-shaped symbol with true
and false branches. The condition placed in the box
is a Boolean expression.
Conditional output box: a box with curved ends;
contains a conditional output list. The conditional
outputs depend on both the state of the system and
the inputs.
© 2018 Cengage Learning®. May not be scanned, copied or duplicated, or posted to a publicly
accessible website, in whole or in part.
5-4
Digital Systems Design Using VHDL Roth/John

SM Charts (continued)

 An SM chart is constructed from SM blocks:

 Each one contains exactly one state box, together
with the decision boxes and conditional output
boxes.
 An SM block has one entrance path and one or more
exit paths.
 Each SM block describes the machine operation
during the time that the machine is in one state.

© 2018 Cengage Learning®. May not be scanned, copied or duplicated, or posted to a publicly
accessible website, in whole or in part.
5-5
Digital Systems Design Using VHDL Roth/John

SM Charts (continued)
Example of an SM block:

© 2018 Cengage Learning®. May not be scanned, copied or duplicated, or posted to a publicly
accessible website, in whole or in part.
5-6
Digital Systems Design Using VHDL Roth/John

SM Charts (continued)
Conditions in the decision boxes are
evaluated to determine which paths are
followed through the SM block.
When a conditional output box is encountered
along a path, the corresponding conditional
outputs become true.
If an output is not encountered along a path,
that output is false by default.
A path through an SM block from entrance to
exit is referred to as a link path.
© 2018 Cengage Learning®. May not be scanned, copied or duplicated, or posted to a publicly
accessible website, in whole or in part.
5-7
Digital Systems Design Using VHDL Roth/John

SM Charts (continued)
Two equivalent SM blocks:
 In both (a) and (b), the output Z2 = 1 if
X1 = 0; the next state is S2 if X2 = 0 and S3 if
X2 = 1.

© 2018 Cengage Learning®. May not be scanned, copied or duplicated, or posted to a publicly
accessible website, in whole or in part.
5-8
Digital Systems Design Using VHDL Roth/John

SM Charts (continued)
Rules for creating an SM block:
For every valid combination of input variables,
there must be exactly one exit path defined.
No internal feedback within a block is allowed.

© 2018 Cengage Learning®. May not be scanned, copied or duplicated, or posted to a publicly
accessible website, in whole or in part.
5-9
Digital Systems Design Using VHDL Roth/John

Derivation of SM Charts
The method used to derive an SM chart for a
sequential control circuit is similar to that
used to derive the state graph:
1. Draw a block diagram of the system one is
controlling.
2. Define the required input and output signals
to the control circuit.
3. Construct an SM chart that tests the input
signals and generates the proper sequence of
output signals.

© 2018 Cengage Learning®. May not be scanned, copied or duplicated, or posted to a publicly
accessible website, in whole or in part.
5-10
Digital Systems Design Using VHDL Roth/John

Derivation of SM Charts:
Binary Multiplier Example
Conversion of an SM
chart to a VHDL
process:
A case statement can
be used to specify
what happens in each
state. Each condition
box corresponds
directly to an if
statement (or an elsif).

© 2018 Cengage Learning®. May not be scanned, copied or duplicated, or posted to a publicly
accessible website, in whole or in part.
5-11
Digital Systems Design Using VHDL Roth/John

Derivation of SM Charts:
Binary Multiplier (continued)
Two processes are used for VHDL code:
 1. Represents the combinational part of the circuit.
 2. Updates the state register on the rising edge of the
clock.
The signals Load, Sh, and Ad are turned on in the
appropriate states, and they must be turned off
when the state changes.
 A way to do this is to set them all to 0 at the start of the
process.

© 2018 Cengage Learning®. May not be scanned, copied or duplicated, or posted to a publicly
accessible website, in whole or in part.
5-12
Digital Systems Design Using VHDL Roth/John

Derivation of SM Charts:
Binary Multiplier (continued)

© 2018 Cengage Learning®. May not be scanned, copied or duplicated, or posted to a publicly
accessible website, in whole or in part.
5-13
Digital Systems Design Using VHDL Roth/John

Derivation of SM Charts:
Binary Multiplier (continued)

© 2018 Cengage Learning®. May not be scanned, copied or duplicated, or posted to a publicly
accessible website, in whole or in part.
5-14
Digital Systems Design Using VHDL Roth/John

Realization of SM Charts
Methods used to realize SM charts are similar
to those used to realize state graphs.
Realization will consist of a combinational
subcircuit, together with flip-flops for storing
the state of the circuit.
It is difficult to eliminate redundant states in
an SM chart, as the chart is usually
incompletely specified. Also, combining states
may make the SM chart more difficult to
interpret.

© 2018 Cengage Learning®. May not be scanned, copied or duplicated, or posted to a publicly
accessible website, in whole or in part.
5-15
Digital Systems Design Using VHDL Roth/John

Realization of SM Charts
(continued)
Before deriving next-state and output
equations from an SM chart, a state
assignment must be made.
Techniques include one‑hot state assignment or
encoded state assignment.

© 2018 Cengage Learning®. May not be scanned, copied or duplicated, or posted to a publicly
accessible website, in whole or in part.
5-16
Digital Systems Design Using VHDL Roth/John

Realization of SM Charts: Binary

Multiplier Controller
SM Chart for multiplier controller:

© 2018 Cengage Learning®. May not be scanned, copied or duplicated, or posted to a publicly
accessible website, in whole or in part.
5-17
Digital Systems Design Using VHDL Roth/John

Realization of SM Charts: Binary

Multiplier Controller (continued)
We can realize this SM chart with two D flip-flops
and a combinational circuit. Assume that the state
assignments are:
 AB = 00 for S0, AB = 01 for S1, AB = 10 for S2, and AB =
11 for S3.
 Logic equations are derived by tracing link paths on the
SM chart and then simplifying the resulting equations.
 Load = A’B’St
 Sh = A’BM’(K’ + K) + AB’(K’ + K) = A’BM’ + AB’
 Ad = A’BM
 Done = AB

© 2018 Cengage Learning®. May not be scanned, copied or duplicated, or posted to a publicly
accessible website, in whole or in part.
5-18
Digital Systems Design Using VHDL Roth/John

Realization of SM Charts: Binary

Multiplier Controller (continued)
Next state equations can be derived by
inspection of the SM chart and considering the
state assignments.
A+ = A’BM’K + A’BM + AB’K = A’B(M + K) + AB’K
B+ = A’B’St + A’BM’(K’ + K) + AB’(K’ + K) =
A’B’St + A’BM’ + AB’
The multiplier controller can be implemented in
a hardwired fashion by two flip-flops and a few
logic gates. Can be implemented with discrete
gates or in a PLA, CPLD, or FPGA.

© 2018 Cengage Learning®. May not be scanned, copied or duplicated, or posted to a publicly
accessible website, in whole or in part.
5-19
Digital Systems Design Using VHDL Roth/John

Realization of SM Charts: Binary

Multiplier Controller (continued)
State transition table:
Each row in the table corresponds to one of the
link paths in the SM chart. Outputs can be
derived by tracing the corresponding link paths.

© 2018 Cengage Learning®. May not be scanned, copied or duplicated, or posted to a publicly
accessible website, in whole or in part.
5-20
Digital Systems Design Using VHDL Roth/John

Realization of SM Charts: Binary

Multiplier Controller (continued)
The design may also be implemented with
ROM, and the size can be calculated by
considering:
5 different inputs to the combinational circuit.
Thus, 32 entries.
The combinational circuit should generate 6
signals. Hence, each entry has to be 6 bits
wide.
Thus, this design can be implemented using a
32 x 6 ROM and two D flip-flops.

© 2018 Cengage Learning®. May not be scanned, copied or duplicated, or posted to a publicly
accessible website, in whole or in part.
5-21
Digital Systems Design Using VHDL Roth/John

Realization of SM Charts: Binary

Multiplier Controller (continued)
If a ROM is used, the table must be expanded
to 25 = 32 rows. Dashes must be replaced
with all combinations of 0’s and 1’s. If a row
has n dashes, it must be replaced by 2n rows.
Ex: 5th row of previous table replaced with:

© 2018 Cengage Learning®. May not be scanned, copied or duplicated, or posted to a publicly
accessible website, in whole or in part.
5-22
Digital Systems Design Using VHDL Roth/John

Microprogramming
The previous method was hardwiring,
indicating that control signals are generated
by fixed logic circuitry.
Proposed by Maurice Wilkes in 1951,
microprogramming is building a special
computer for executing the algorithmic flow
chart describing the controller of a system.
Early microprocessors such as the Intel 8086
and Motorola 68000 were microprogrammed.

© 2018 Cengage Learning®. May not be scanned, copied or duplicated, or posted to a publicly
accessible website, in whole or in part.
5-23
Digital Systems Design Using VHDL Roth/John

Microprogramming (continued)
One should be able to realize the controller by
just “sequencing” through the memory. For
this reason, microprogrammed controllers are
also often called sequencers.
Control store or microprogram memory:
the memory that stores the control words.
Advantages of microprogramming:
Debugging is simple.
System modifications are easy.
Errors can be found and corrected easily.

© 2018 Cengage Learning®. May not be scanned, copied or duplicated, or posted to a publicly
accessible website, in whole or in part.
5-24
Digital Systems Design Using VHDL Roth/John

Microprogramming (continued)
Disadvantages:
It is slow.
The complexity of the microprocessors led to the
reduced instruction set computing (RISC)
era.
RISC microprocessors are simpler, have fewer
memory-addressing modes, and need simpler
control units.
Today, microprogramming may be used only for
microprocessors with complex instruction set
architectures (ISAs).
© 2018 Cengage Learning®. May not be scanned, copied or duplicated, or posted to a publicly
accessible website, in whole or in part.
5-25
Digital Systems Design Using VHDL Roth/John

Microprogramming (continued)
General idea of microprogramming:
Store a control word (or microinstruction)
corresponding to each state.
The microinstruction specifies the outputs to be
generated and where the next microinstruction
can be found. Corresponds to state transitions
in the state diagram or SM chart.

© 2018 Cengage Learning®. May not be scanned, copied or duplicated, or posted to a publicly
accessible website, in whole or in part.
5-26
Digital Systems Design Using VHDL Roth/John

Microprogramming: Two-Address
Microcode
A typical hardware arrangement for
microprogramming:

© 2018 Cengage Learning®. May not be scanned, copied or duplicated, or posted to a publicly
accessible website, in whole or in part.
5-27
Digital Systems Design Using VHDL Roth/John

Microprogramming: Two-Address
Microcode (continued)
SM Chart Transformations for
Microprogramming:
To facilitate easy and efficient
microprogramming.
Transform the SM chart such that only one entry
is required per state.
Microprogram size is significantly smaller than
the ROM size in a naïve LUT method.
Eliminate Conditional Outputs:
Convert state diagram or SM chart into a Moore
state machine for easy microprogramming.
© 2018 Cengage Learning®. May not be scanned, copied or duplicated, or posted to a publicly
accessible website, in whole or in part.
5-28
Digital Systems Design Using VHDL Roth/John

Microprogramming: Two-Address
Microcode (continued)
Allow Only One Qualifier per State:
Qualifiers: inputs that are tested in each state
of the state machine.
It is simpler to implement microprogramming
when only one variable is tested in each state.
 Transformations on SM charts to facilitate easy
microprogramming:
 I. Eliminate all conditional outputs by transforming to a
Moore machine.
 II. Test only one input (qualifier) in each state.

© 2018 Cengage Learning®. May not be scanned, copied or duplicated, or posted to a publicly
accessible website, in whole or in part.
5-29
Digital Systems Design Using VHDL Roth/John

Microprogramming: Two-Address
Microcode (continued)
Example: transform the SM chart of the
multiplier:

© 2018 Cengage Learning®. May not be scanned, copied or duplicated, or posted to a publicly
accessible website, in whole or in part.
5-30
Digital Systems Design Using VHDL Roth/John

Microprogramming: Two-Address
Microcode (continued)
Eliminate/combine redundant states/tasks.
Improved SM chart:

© 2018 Cengage Learning®. May not be scanned, copied or duplicated, or posted to a publicly
accessible website, in whole or in part.
5-31
Digital Systems Design Using VHDL Roth/John

Microprogramming: Two-Address
Microcode (continued)
The microprogram will look as it does in the table
below, assuming a straight binary state
assignment.

Since there are six states, three flip-flops will be

required. The ROM will need six entries. Each entry
will need 12 bits. ABC: the address at which the
microinstruction is stored.
© 2018 Cengage Learning®. May not be scanned, copied or duplicated, or posted to a publicly
accessible website, in whole or in part.
5-32
Digital Systems Design Using VHDL Roth/John

Microprogramming: Two-Address
Microcode (continued)
Since there are three inputs, a 4-to-1 MUX
will be sufficient to select the appropriate
qualifier.

© 2018 Cengage Learning®. May not be scanned, copied or duplicated, or posted to a publicly
accessible website, in whole or in part.
5-33
Digital Systems Design Using VHDL Roth/John

Microprogramming: Single-Address
Microcode
Control flows in a default
sequence except when
branch and jump
instructions alter the flow.
If the qualifier is false, next
state should be current
state plus one.
The next state when the
qualifier is true is the only
next state explicitly
specified in the microcode.
© 2018 Cengage Learning®. May not be scanned, copied or duplicated, or posted to a publicly
accessible website, in whole or in part.
5-34
Digital Systems Design Using VHDL Roth/John

Microprogramming: Single-Address
Microcode (continued)
Modified SM chart for binary multiplier:

© 2018 Cengage Learning®. May not be scanned, copied or duplicated, or posted to a publicly
accessible website, in whole or in part.
5-35
Digital Systems Design Using VHDL Roth/John

Microprogramming: Single-Address
Microcode (continued)
Microprogram and MUX for single-address
(minimum number of states used):

Single-address consists of six entries of 9 bits

each.

© 2018 Cengage Learning®. May not be scanned, copied or duplicated, or posted to a publicly
accessible website, in whole or in part.
5-36
Digital Systems Design Using VHDL Roth/John

Linked State Machines

When a sequential machine becomes large,
divide it into several smaller machines that
are linked together.
Each of the smaller machines is easier to
design and implement. Also, one of the
submachines may be “called” in several
different places by the main machine.

© 2018 Cengage Learning®. May not be scanned, copied or duplicated, or posted to a publicly
accessible website, in whole or in part.
5-37
Digital Systems Design Using VHDL Roth/John

Linked State Machines (continued)

SM chart for serially linked state machines:

© 2018 Cengage Learning®. May not be scanned, copied or duplicated, or posted to a publicly
accessible website, in whole or in part.
5-38
Digital Systems Design Using VHDL Roth/John

Summary
SM Chart:
Equivalent to a state graph, but usually easier to
understand the system operation by review of the
SM chart.
Differs from a regular flowchart since different
rules must be followed.
Examples of derivation of SM charts include the
binary multiplier and a dice game.
Instead of using an SM chart, one could
construct an equivalent state graph from the
flowchart.
© 2018 Cengage Learning®. May not be scanned, copied or duplicated, or posted to a publicly
accessible website, in whole or in part.
5-39
Digital Systems Design Using VHDL Roth/John

Summary (continued)
Procedures for digital system design
presented include:
Block diagram
Flowchart
SM Chart or State Graph
Behavioral VHDL description
Test bench
Implementation (hard-wiring and
microprogramming)

© 2018 Cengage Learning®. May not be scanned, copied or duplicated, or posted to a publicly
accessible website, in whole or in part.
5-40
Digital Systems Design Using VHDL Roth/John

Summary (continued)
Techniques for implementing control units:
Hardwiring:
 The control signals are generated using fixed
(hardwired) logic circuitry.
 Results in faster systems, because hardwired control
signals are generated by logic gates and they are
typically faster than memory.

© 2018 Cengage Learning®. May not be scanned, copied or duplicated, or posted to a publicly
accessible website, in whole or in part.
5-41
Digital Systems Design Using VHDL Roth/John

Summary (continued)
Techniques for implementing control units
(continued):
Microprogramming:
 Control words are stored in the microprogram memory.
 The size of the microprogram is reduced by
transforming the SM chart into a form in which only
one input is tested in each state.
 Results in slower systems.

For complex systems, we can split the control

unit into several sections by using linked state
machines.
© 2018 Cengage Learning®. May not be scanned, copied or duplicated, or posted to a publicly
accessible website, in whole or in part.
5-42