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Sufjan Misini - 220307119
Sufjan Misini - 220307119
Brock J. LaMeres - Introduction to Logic Circuits & Logic Design ëith VHDL, 2019, USA.
Input Output
A B C F0 f1 f2 f3
0 0 0 1 0 1 0
0 0 1 1 0 1 1
0 1 0 1 1 0 1
0 1 1 0 1 1 1
𝐴 𝐵+ 𝐵 𝐶
1 0 0 0 0 0 0
1 0 1 0 1 0 1
1
1
1
1
0
1
1
0
1
1
0
1
0
1
𝐹 0∑ 𝑚 ( 0,1,2,6) =𝐴𝐵+𝐵𝐶
© Çlrim Allaqi, Alpet Gexha, Sufjan Misini
Projektimi i qarkut logjikë
Input Output
A B C F0 f1 f2 f3
0 0 0 1 0 1 0
1 1
0 0 1 1 0 1 1 1 1 1
0 1 0 1 1 0 1
0 1 1 0 1 1 1
1 0 0 0 0 0 0
1 0 1 0 1 0 1 𝑨𝑪 + 𝑩
Input Output
A B C F0 f1 f2 f3
0 0 0 1 0 1 0
0 0 1 1 0 1 1
0 1 0 1 1 0 1
0 1 1 0 1 1 1
1 0 0 0 0 0 0
𝐴 𝐵+ 𝐵𝐶
1 0 1 0 1 0 1
𝐹 2 ∑ 𝑚 ( 0,1,3,7 )= 𝐴𝐵+𝐵𝐶
1 1 0 1 1 0 0
1 1 1 0 1 1 1
Input Output
1
A B C F0 f1 f2 f3
0 0 0 1 0 1 0
1 1 1 1
0 0 1 1 0 1 1
0 1 0 1 1 0 1
0 1 1 0 1 1 1
1 0 0 0 0 0 0
𝑪+ 𝑨 𝑩
1 0 1 0 1 0 1
𝐹 3 ∑ 𝑚 ( 1,2,3,5,7 )=𝐶+ 𝐴 𝐵
1 1 0 1 1 0 0
1 1 1 0 1 1 1
F=
F=
F=
F=
F=
F=
F=
F=