INVENTIVE CONFIDENTIAL

Is Co-existence Possible?

David White
 Virtual Manufacturing Use Model

Calibration Step Prediction Step

Data from ECD
& CMP
Processing ECD/CMP
Fabricate Measurement Virtual Mfg
Results
Test Wafer Data From Process Library
(ECP/CMP) Test Wafer

Product
Test Wafer Design Geometry Predict
Design Geometry Calibrate Layout
Extraction
Extraction New Design
Layout File Model File

Full-Chip
Prediction
Semi-Physical Tailored to
Model Tailored to ECD/CMP Customer’s
Specific Process Virtual Mfg Process & Design
Process Library Topographical
Analysis

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 What Are Pattern-Process Interactions
Structures with Same Line widths, Same Local Density,
and Same Polish Conditions Have Very Different Cu Loss

Memory

Analog
IP Blocks
Rotated
High
IP Block
CPU
Block
Thickness

Low
IITC 2005, Nagaraj NS: “Copper and Low k
Scaling Challenges: A Design Perspective”

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Accounting For Variation in Design Process

Actual Thickness
+20%

Systematic Systematic &

Thickness Random
Manufacturing Thickness
Variation Manufacturing
Guardband Variation
Guardband
-20%

Current “2D” Methodology is Conservative Full Chip Guardband

for Both Systematic and Random Thickness Variation (+- 20%)

Random
+10% Thickness
Actual Thickness Manufacturing
-10% Variation
Guardband

Cadence “3D” Methodology Eliminates Systematic Guardband

Leaving Only a Relatively Small Random Thickness Variation (+- 10%)

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 Experimental Results: CMP Aware Routing
CMP variation
1
• On average 7.5% reduction
Normalized Variation

0.98
0.96
0.94 • Up to 10.1% reduction
0.92
0.9
0.88
0.86
0.84
ibm01 ibm03 ibm05 ibm07 ibm09

BoxRouter Wire density

Timing
1
0.98 • On average 7% reduction
Normalized timing

0.96
0.94 • Up to 10% reduction
0.92
0.9
0.88
0.86
0.84
ibm01 ibm03 ibm05 ibm07 ibm09 [Cho et al, ICCAD’06]
BoxRouter Wire density

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 Rules versus Models as Function of
Pattern-Process Dependent Interaction

Non-linear, multi-dimensional process or system

MORE
(Volumes) HIGH

Value of Models
Value of Rules

Complexity Complexity

LESS
LOW

LOCAL Process Interaction GLOBAL

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 Deficiencies with Pure Rules Based Approach

Little Value Back

Characterization of to Manufacturing
Results in Pattern-Process
Loss of Behavior
Accuracy Manufacturing
Capturing all
meaningful Customer
interactions into rules

Pattern Design Violations & Design

Geometries Rules Scoring Metrics Tools

Local versus
global
interactions
Design
Customer

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 Deficiencies with Pure Model Based Approach

Significant Value Back

to Manufacturing
Characterization of
Pattern-Process
Behavior
Manufacturing
Customer

No Filtering
of Data
Speed? Volumes
Pattern Process Design
Models of Data Tools
Geometries (width and thickness
e.g. 25M
dimensions) thickness What to
values
do with
Why does speed have question mark? Data?
To be addressed later How does
it impact
Results in my
design?
Speed and Design
Data Issues Customer

8 June 24, 2023 Cadence Confidential: Cadence Internal Use Only

 Rules and Models Not Mutually Exclusive
Significant Value Back
Characterization of to Manufacturing
Pattern-Process
Behavior
Manufacturing
Customer

Volumes
Global Pattern Process Accuracy
Models of Data
Geometries (width and thickness
dimensions)

Local Pattern Design Violations & Design

Speed
Geometries Rules Scoring Metrics Tools

Design
Customer

9 June 24, 2023 Cadence Confidential: Cadence Internal Use Only

 65nm Rule Deck Example
• Ran three separate 65nm rule decks on 65nm production design
• 96% of operation counts are done with 0 halo size
• Density rules using 100 micron window size are less than 1% of
overall operations but 5% of overall execution time
100%
90%
80%
70% 100%
90%
60%
80% % Operation Counts
50%
70% % Execution Time
40% 60%
30% 50%

20% 40%
30%
10%
20%
0%
10%
0%

Halo Size
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 Backup / Q&A

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 Models Complement Rules
Design Rules Say OK, Models Say Its Not Acceptable

Metal 4 Copper Density Metal 4 Copper Loss

0.70  1200A

0.70  2500A

• Both Areas Have 70% Average

Density
• But Very Different Copper Loss

1200A 2500A

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 Process for Forming Interconnect (Wires)

Features Defined Through

Lithography and Etch
dielectric

copper
ECD Copper Plating

Step 1: Copper Plating

dielectric

Copper CMP (Bulk)

Step 2: Bulk Polish

Copper CMP (Touchdown)

Step 3: Copper Clear or Touchdown

Copper CMP (Barrier)

Step 4: Barrier Removal

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 Rules versus Models as Function of
Uncertainty in Process Characterization

Non-linear, multi-dimensional process or system

MORE
(Volumes) HIGH

Value of Models
Value of Rules

LESS
LOW
POORLY WELL
CHARACTERIZED
UNSTABLE PROCESS
Process Maturity CHARACTERIZED
STABLE PROCESS

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 Chemical Mechanical Polishing

Force

Modern polishing
heads have separate
rings where the force
can be radially
adjusted

Table with Pad Rotating

Within-Chip Variation: dominated by layout, pad and slurry interaction

Within-Wafer Variation: dominated by pressure zone apportionment in
carrier and relative velocities of carrier and table
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 Interconnect Variation
Wafer Level
Variation
Wafer
Surface
• Within-Chip Variation is Huge!
– Thickness Variation: 10% to 30%
– Width Variation: 10% to 30%
• Due to Design Impact on Manufacturing
– Varying Feature Density
– Varying Feature Widths
• Variation Leads to Over-Compensation in Design
– Timing Failures
– Decreased Performance Chip
– Increased Power Consumption Surface
Within-Chip
Variation
Oxide Loss Dishing Erosion Total Copper Loss

Isolated Isolated Dense Array Dense Array

Thin-Lines Wide-Lines Thin-Lines Wide-Lines

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