I/O Ports

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Port registers ( P0, P1, P2, P3)

 Four I/O ports of 8051 has its own register,

designated as the name of the concerned port (P0, P1,
P2, P3).
 System communicates with these ports through these
registers.
 Data should be written in these registers to send it out
through ports.
 To get the incoming data from these ports, these port
registers are to be read.
 All four port SFRs are bit addressable.

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3
Architecture of 8051 ports

 The architecture of every port is related to its duties.

 There is a marginal difference between different
ports.
 Port 0
▪ Outputs lower 8-bit address
▪ Send/receive 8-bit data
▪ I/O port
 Port 2
▪ Outputs upper 8-bit address
▪ I/O port

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 Port 3
▪ Alternate function signals
▪ I/O port
 Port 1
▪ I/O port
 Port 0 is truly bi-directional port
 Other ports are quasi-bi-directional ports.

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Internal architecture of Port 0 pin

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Internal architecture of Port 1 pin

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Internal architecture of Port 2 pin

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Internal architecture of Port 3 pin

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Output latch

 The output data at D is

latched at Q with the
transition of the clock
input.
 This latched output
data would be available
through Q and Q till a
fresh clock transition
with a different data.

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FET pull-up at output
 If the data written in port
latch is ‘1’ the Q outputs
‘0’ which turns the FET(FL)
off. So, at output pin the
data available would be ‘1’.

 If the data written in port

latch is ‘0’ the Q outputs
‘1’ which turns the FET(FL)
on. So, at output pin the
data available would be ‘0’.

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Read buffer for port pin
 To implement the reading
mechanism through the same port
pin, an extra buffer is introduced,
between port pin and the internal
data bus.
 ‘READ PIN’- control for reading
the input buffer. When activated,
port-pin data is directly available
at the internal data bus, provided
that FET(FL) is off.

 If this FET is on, then irrespective

of the input condition at the port
pin, a logic’0’ would be available
at the internal data bus, which is
not desirable.
To switch off the FET(FL), a ‘1’ must be written at the D FF, before the port pin-
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reading operation. This is very important.
Read output latch
 At many times, it is necessary to
read the output data (for
modification of present output or
other purposes); another buffer is
connected with the internal data
bus of the system, which takes
its input from the Q output of the
D-FF.
 ‘READ LATCH’ command is
necessary to read the current
value from this latch.
 So, two types of reading are
possible in 8051 ports.
 Reading the port pin
 Reading the output latch

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For easier comparison and
understanding

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External code memory
WR
RD
PSEN OE
ALE 74LS373 CS
G
P0.0 A0
D
P0.7 A7

D0
D7
EA
P2.0 A8
P2.7 A15

8051 ROM
External data memory
WR WR
RD RD
PSEN
ALE 74LS373 CS
G
P0.0 A0
D
P0.7 A7

D0
D7
EA
P2.0 A8
P2.7 A15

8051 RAM