Semiconductor Devices

EE203

Field Effect Transistors

(MOSFETs)
Module 4
Outline

• The ideal MOS Structure

• Capacitance of the MOS System
• CV of MOS System; Ideal, effect of oxide and
interface charge
• Structure and operation of MOSFET devices
• Improved Models for Short-Channel MOSFETs
• Devices based on MOSFET

EE311 2
FETs
Field Effect Transistors

Billions of MOSFETs are in the silicon chips of every smartphone, tablet, laptop, desktop and power hungry data
centre. Without the MOSFET, the chips and the corresponding electronic devices there will be no internet, world wide
web, Google, Facebook, Instagram, Tweeter, WhatsApp, digital economy, on line shopping…  In the last few decades
the MOSFET has completely transform the economy, the society and us as humans. We still do not understand in full
the magnitude and the consequences of this transformation.

EE311 3
Source: Sze
FETs
Junction FET Metal-Oxide FET

CMOS
MODFET

The 1-T DRAM cell is now the most w man-made object on this planet earth.

EE311 4
Source: Pierret, Google
FETs

EE311 5
Source: Sze
MOS system

EE311 6
Source: Nanohub
MOS system

EE311 7
Source: Sze
MOS
MOS Interface Physics: Flat band conditions

EE311 8
Source: Baliga
MOS
MOS Interface Physics: Accumulations

EE311 9
Source: Baliga
MOS
MOS Interface Physics: Depletion

EE311 10
Source: Baliga
Forward Conduction
MOS Interface Physics: Inversion

EE311 11
Source: Baliga
Forward Conduction
MOS Surface Charge Analysis

Potential Distribution within the MOS structure operating under inversion conditions
EE311 12
Source: Baliga
Forward Conduction
MOS Surface Charge Analysis

EE311 13
Source: Mishra and Singh
Forward Conduction
MOS Charge Analysis

Since charge neutrality exists in the bulk of the

semiconductor far removed from the oxide interface

EE311 14
Source: Baliga
Forward Conduction

Debye length – distance at which charge fluctuations are screened out

to look like neutral entities

EE311 15
Source: Baliga
Forward Conduction
MOS Interface Physics
Total space charge per unit area within the semiconductor

Electric field at the semiconductor surface

EE311 16
Source: Baliga
Forward Conduction

Strong Inversion
Accumulation

Depletion
Weak Inversion

EE311 17
Source: Baliga
Forward Conduction
MOS Interface Physics

EE311 18
Source: Baliga
Forward Conduction
MOS Interface Physics

EE311 19
Source: Baliga
Forward Conduction
Spatial Carrier Distribution
Under Inversion

Shared!!

EE311 20
Source: Baliga
Forward Conduction
Maximum Depletion Width
defined by the on-set of strong inversion conditions.

EE311 21
Source: Baliga
Forward Conduction
Threshold Voltage

The voltage applied to the metal electrode of the MOS structure is shared between the oxide
and the semiconductor

The threshold voltage (V TH ) is defined as the voltage applied to the metal electrode to enter
the strong inversion domain of operation.

EE311 22
Source: Baliga
Forward Conduction

High tox leads to high Vth

EE311 23
Source: Baliga
Forward Conduction
Non-idealities
1. Negative work function difference
Use of polysilicon

EE311 24
Source: Baliga
Forward Conduction

EE311 25
Source: Baliga
Forward Conduction
2. Oxide Charges

EE311 26
Source: Baliga
Forward Conduction

EE311 27
Source: Baliga
Forward Conduction

EE311 28
Source: Baliga
Forward Conduction

EE311 29
Source: Baliga
Forward Conduction

EE311 30
Forward Conduction

EE311 31
Source: nanohub.org
CV

EE311 32
Source: Neaman
CV

EE311 33
Source: Neaman
Forward Conduction
Channel Resistance

EE311 34
Source: Baliga
Forward Conduction

EE311 35
Source: Baliga
Forward Conduction

EE311 36
Source: Baliga
Forward Conduction

EE311 37
Source: Baliga
Forward Conduction

EE311 38
Source: Baliga
Forward Conduction
Linear region of operation, VD << VG

RCH can be decreased by VG, but limited due to mobility degradation.

Independent of VG

EE311 39
Source: Baliga
Forward Conduction
Sublinear region of operation, VD ~ VG

Reduction of inversion layer charge, pinch-off

Independent of VD, o/p impedance infinite in magnitude

• Proportional to the gate bias voltage and independent of the drain bias voltage.
• The dependence of the transconductance on the gate bias voltage is a
fundamental nonlinearity inherent in MOSFET structures that operated with
current saturation due to channel pinch-off.

EE311 40
Source: Baliga
Forward Conduction

EE311 41
Source: Baliga
Forward Conduction

EE311 42
Source: Baliga
 Sub-Threshold Swing, S
log ID

Inverse slope is
subthreshold swing, S
[mV/dec]
NMOSFET Energy Band Profile VGS
0 VT
n(E)  exp(-E/kT)
increasing E

Source increasing
VGS Drain

distance
Forward Conduction

EE311 44
Source: Sze
 MOSFET Small Signal Model
(Saturation Region)
• Conductance parameters:
A small change in VG or VDS will result
in a small change in ID

low-frequency:

high-frequency:

R. F. Pierret, Semiconductor Device Fundamentals, Fig. 17.12

MOSFET Capacitances

 CGS and CGD are intrinsic capacitances

 COS and COD are parasitic capacitances

 CjS and CjD are reverse-biased p-n junction capacitance

EE311 46
Source:
 MOSFET Cutoff Frequency, fT
The cut-off frequency fT is defined as the frequency when the
current gain is reduced to 1.
input current = vG here is ac signal
CG is approximately equal to the
output current = gate capacitance,  W L Cox

At the cutoff frequency (wT = 2pfT):

® Higher MOSFET operating frequency is achieved by

decreasing the channel length L
Short Channel Effects

EE311 48
Source: Baliga
Short Channel Effects
Threshold Voltage Roll-off in Linear Region

EE311 49
Source: Sze
Short Channel Effects
Drain-Induced Barrier Lowering (DIBL)

EE311 50
Source: Sze
 Channel Length Modulation
• As VDS is increased above VDsat, the width DL of the depletion
region between the pinch-off point and the drain increases,
i.e. the inversion layer length decreases.
If DL is significant compared to L,
then IDS will increase slightly with
increasing VDS>VDsat, due to “channel-
length modulation”

IDS

VDS
R. F. Pierret, Semiconductor Device Fundamentals, Figs. 17.2, 17-3
Short Channel Effects
Scaling Rules

EE311 52
Source: Sze
 CMOS Devices and Circuits
CIRCUIT SYMBOLS CMOS INVERTER CIRCUIT
N-channel P-channel VDD VOUT INVERTER
MOSFET MOSFET S LOGIC SYMBOL
VDD
D
VIN VOUT
D

S VIN
GND
0 VDD

• When VG = VDD , the NMOSFET is on and the PMOSFET is off.

• When VG = 0, the PMOSFET is on and the NMOSFET is off.

EE130/230A Fall 2013 Lecture 19, Slide 53

“Pull-Down” and “Pull-Up” Devices
• In CMOS logic gates, NMOSFETs are used to connect
the output to GND, whereas PMOSFETs are used to
connect the output to VDD.
– An NMOSFET functions as a pull-down device when it is
turned on (gate voltage = VDD)
– A PMOSFET functions as a pull-up device when it is turned
on (gate voltage = GND) VDD
A1
Pull-up
input signals A2 PMOSFETs only
network
…

AN
F(A1, A2, …, AN)
A1
Pull-down
A2 NMOSFETs only
network
…

AN
EE130/230A Fall 2013 Lecture 19, Slide 54
 CMOS NAND Gate
VDD A B F
0 0 1
0 1 1
1 0 1
1 1 0
A B

F
A

EE130/230A Fall 2013 Lecture 19, Slide 55

 CMOS NOR Gate
VDD
A B F
0 0 1
0 1 0
A 1 0 0
1 1 0

B A

EE130/230A Fall 2013 Lecture 19, Slide 56

 CMOS Pass Gate
A

X Y Y = X if A

EE130/230A Fall 2013 Lecture 19, Slide 57

Forward Conduction
The on-resistance (RON ) for a power MOSFET structure is defined as the total resistance
to current flow between the drain and source electrodes when a gate bias is applied to turn
on the device.
The on-resistance limits the maximum current handling capability of the power MOSFET
structure.

EE311 58
Source: Baliga
Characteristics: Static

EE311 59
Source: Toshiba Corporation
Capacitance Characteristics

EE311 60
Source: Toshiba Corporation
dv/dt capability
When the drain-source voltage is raised sharply at the turn-on of a MOSFET, a displacement
current flows to the PN junction capacitance (C) between drain and source, due to the rate of
voltage change dv/dt.

EE311 61
Source: Toshiba Corporation
Switching Characteristics
Power MOSFETs are majority-carrier devices, they are faster and capable of switching at higher
frequencies than bipolar transistors.

EE311 62
Source: Toshiba Corporation
Characteristics: Dynamic

EE311 63
Source: Toshiba Corporation
Thank you!!

EE311 64
Forward Conduction

EE311 65
Source: Baliga
Ideal specific on-resistance

EE311 66
Source: Baliga
Ideal specific on-resistance

EE311 67
Source: Baliga
Blocking Voltage

• Impact of Edge Termination

• Impact of Graded Doping Profile
• Impact of Parasitic Bipolar Transistor
• Impact of Cell Pitch
• Impact of Gate Shape
• Impact of Cell Surface Topology

EE311 68
Source: Baliga
Blocking Voltage

EE311 69
Source: Baliga
Blocking Voltage

EE311 70
Source: Baliga
Blocking Voltage

Source: Liang et. al., Power Microelectronics EE311 71

Capacitance Characteristics
Effective output capacitance (energy-related)

• Co(er) is the effective output capacitance (energy-related) dependent on the drain voltage.

• Power loss occurs at the turn-on and turn-off of the MOSFET due to the charging and
discharging of the output capacitance.

C(v) is a function of the VDS-dependent output capacitance Coss.

EE311 72
Source: Toshiba Corporation
Device Structure and Operation

EE311 73
Source: Baliga
Device Structure and Operation

EE311 74
Source: Baliga
Device Structure and Operation

Source: https://www.digikey.com/en/articles/techzone/2017/sep/working-sic-mosfets-challenges-design-recommendations

EE311 75
Device Structure and Operation

Source: IEEE ELECTRON DEVICE LETTERS, VOL.EE311

40, NO. 3, MARCH 2019 76
Device Structure and Operation

EE311 77
Source: Baliga
Device Structure and Operation

EE311 78
Source: Baliga
Device Structure and Operation

EE311 79
Source: Baliga
 MOS Capacitor Structure
MOS capacitor • Most MOS devices today employ:
(cross-sectional view) o degenerately doped polycrystalline
Si (“poly-Si”) as the “metallic”
gate-electrode material
GATE - n+-type for “n-channel” transistors
xo - p+-type, for “p-channel” transistors
+ o SiO2 as the gate dielectric
VG _
Semiconductor - band gap = 9 eV
- er,SiO2 = 3.9
o Si as the semiconductor material
- p-type, for “n-channel” transistors
- n-type, for “p-channel” transistors

EE311
Source: Adopted from “Prof. Liu, UC Berkeley” 80
 Bulk Semiconductor Potential, fF

• p-type Si:
Ec

qfF
Ei
EF
Ev
• n-type Si:
Ec
EF |qfF|
Ei
Ev

EE311
Source: Adopted from “Prof. Liu, UC Berkeley” 81
 Special Case: Equal Work Functions
R. F. Pierret, Semiconductor Device Fundamentals, Fig. 16.2

FM = FS

EE311
Source: Adopted from “Prof. Liu, UC Berkeley” 82
General Case: Different Work Functions
R. F. Pierret, Semiconductor Device Fundamentals, Fig. 18.1

E0 E0

E0

E0

EE311
Source: Adopted from “Prof. Liu, UC Berkeley” 83
MOS Band Diagrams: Guidelines
• Fermi level EF is flat (constant with x) within the semiconductor
• Since no current flows in the x direction, we can assume that equilibrium
conditions prevail

• Band bending is linear within the oxide

• No charge in the oxide => dE/dx = 0 so E is constant
=> dEc/dx is constant

• From Gauss’ Law, we know that the electric field strength in the
Si at the surface, ESi, is related to the electric field strength in the
oxide, Eox:

E E E

EE311
Source: Adopted from “Prof. Liu, UC Berkeley” 84
MOS Band Diagram Guidelines (cont’d)

• The barrier height for conduction-band electron flow from

the Si into SiO2 is 3.1 eV
• This is equal to the electron-affinity difference (cSi and cSiO2)

• The barrier height for valence-band hole flow from the Si

into SiO2 is 4.8 eV

• The vertical distance between the Fermi level in the metal,

EFM, and the Fermi level in the Si, EFS, is equal to the applied
gate voltage (assuming that the Si bulk is grounded):

EE311
Source: Adopted from “Prof. Liu, UC Berkeley” 85
MOS Equilibrium Band Diagram
metal oxide semiconductor

n+ poly-Si
SiO2
EC
EC=EFM EFS
p-type Si EV
EV

EE311
Source: Adopted from “Prof. Liu, UC Berekley” 86
 Flat-Band Condition
• The flat-band voltage, VFB, is the applied voltage which
results in no band-bending within the semiconductor.
• Ideally, this is equal to the work-function difference between the
gate and the bulk of the semiconductor: qVFB = FM  FS

EE311
Source: Adopted from “Prof. Liu, UC Berekley” 87
 Voltage Drops in the MOS
• System
In general,

where
qVFB = FMS = FM – FS
Vox is the voltage dropped across the oxide
(Vox = total amount of band bending in the oxide)
fs is the voltage dropped in the silicon
(total amount of band bending in the silicon)

• For example:
When VG = VFB, Vox = fs = 0, i.e. there is no band bending
EE311
Source: Adopted from “Prof. Liu, UC Berkley” 88
 MOS Operating Regions (n-type
Si) V toward more negative values
Decrease G

 the gate electron energy increases relative to that in the Si

decrease VG decrease VG

• Accumulation • Depletion • Inversion

– VG > VFB – VG < VFB • VG < VT
Electrons accumulated Electrons depleted Surface
inverted to p-
at Si surface from Si surface
type

EE311
Source: Adopted from “Prof. Liu, UC Berkley” 89 Fig. 16.5
R. F. Pierret, Semiconductor Device Fundamentals,
 MOS Operating Regions (p-type
Si) increase V increase V G G

VG = VFB VG < VFB VT > VG > VFB

EE311
Source: Adopted from “Prof. Liu, UC Berkley” 90 Fig. 16.6
R. F. Pierret, Semiconductor Device Fundamentals,
MOS system

EE311 91
Source:
MOS system

EE311 92
Source:
MOS system

EE311 93
Source:
MOS system

EE311 94
Source: