Using ncverilog &

SimVision
AND Gate Verilog Code
 Declare inputs & outputs
• Using inbuilt pre-defined Instance “AND”
• Using bit wise operator & Assign Statement

 Steps :
• Create a file named and_gate.v (can be any name)
• Write the code in and_gate.v
• Execute the code from terminal using
ncverilog and_gate.v
• Up on execution we should ensure that no errors
are present in design
Delay Operator - #
 keyword “#” is used to introduce delay in Verilog code

• c
…..
}
# 10
c
…..
}
• In the above code 1 gets executed first, then simulator waits for 10 units of time then runs code 2
Initial & Always Blocks
 Initial Block is used to run the code which needs to be executed only once

• Syntax : initial begin

….
….
end

 Always block is used to run the copy repetitively

• Syntax : always begin

….
….
end
$monitor & $finish
 #monitor is used to observe the nets

• Syntax : $monitor(“time = %d, a= %b”, $time, a)

 #finish is used to stop the simulation

• Syntax : $monitor(“time = %d, a= %b”, $time, a)

$dumpfile & $dumpvars & VCD Files
 To save Data base and signals
AND Gate –Test Bench & General TB Structure

• Step 1: Create Empty Module

• Step 2: declare inputs as reg &

output as wires
• Step 3: Instantiate the Design with
Instance Name

• Step:4 using initial Block & Delay

Keyword apply stimuli to check
the Design
AND Gate - Test Bench & General TB Structure
• Step5 : using key word $finish to end the
simulation

• Step6 : use dumpfile & dumpvars to store

the signals in VCD Format, we can view
these waveforms using sim-vision tool

• Step7(optional): you can monitor the

signals on the terminal also using $monitor
statement
 Steps :
• Create a file named and_gate_tb.v (can be any name)
• Write the test bnehc code in and_gate_tb.v
• Execute the code from terminal using - “ ncverilog and_gate_tb.v”
• Up on execution we should ensure that no errors are present in design
Sim vison Tool – to observe Waveforms
 Steps :
• Type simvision on terminal this open up the tool
• From File  open Data base ( in the form choose Display file of type .VCD)
• Choose and_gate.vcd which is our results data based in Value Change Dump (VCD)Format
Sim vison Tool – to observe Waveforms
 Steps :
• Select and_gate_tb
• Select signals a,b, vout , this will plot the waveforms
• Use signs on the right (= to fit the waveforms to full simulation time, + to zoom in, - to zoom out)