Supplementary Note

Phase Noise Due to DDSM

Recap:
Incorporating DDSM Quantization Noise into the PLL Noise Model
qn,Ref2 vn,PD2/in,PD2 vn,LF 2 qn,VCO2

vtune
qRef + - KPD + HLF(s) + KV/s + qVCO

qfb
• D = N-Div O/P Step Size
+ + 1/N
• In cycles of VCO

• fs = 1/Ts 2
qn,DDSM qn,Div2
• = DDSM sampling rate

( )| |
2 2 2
• m = DDSM order ∆ 1 − 𝑗 𝜔 𝑇 𝑠 2𝑚 2𝜋 1
𝜃 2
𝑛, 𝐷𝐷𝑆𝑀 = ∙ ∙|1 −𝑒 | ∙ ∙
• N = Av (fractional) feedback 12 𝑓 𝑠 𝑁 1 −𝑒
− 𝑗𝜔𝑇 𝑠

division factor
White Quantization DDSM: H(z) Normalization
• w = offset frequency Sampled Phase
Noise over +/- fs/2 BW To Reference Cycle Integration
& Convert to Radians
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Time Domain View of DDSM & N-Divider Output
TRef

Reference
Clock

Feedback
Clock

NAV*TVCO

TVCO
• On average when the PLL is locked, there are cycles of TVCO per Reference clock cycle
• A 3rd order DDSM will vary the actual number in an individual Reference clock cycle over the range:
•[
• The time location of the N-Divider output positive edge is adjusted in steps of T VCO
 DDSM Step Size  Phase Error Step Size
• Let’s say that the Feedback division sequence follows this sequence:
• …, Nint+2, Nint-1, Nint+0, Nint+4, Nint-3, Nint+1, …
k k+1 k+2 k+3 k+4

• Assuming a fixed frequency input clock to the N-Divider:

• Between the kth and k+1th division cycle, the phase of the N-Divider o/p advances by 3*TVCO (in
terms of time location of the next positive edge)
• Between the k+1th and k+2th division cycle, the phase of the N-Divider o/p retards by 1*TVCO
• Between the k+2th and k+3th division cycle, the phase of the N-Divider o/p retards by 4*TVCO
• Between the k+3th and k+4th division cycle, the phase of the N-Divider o/p advances by 7*TVCO
• and so on…
DDSM Step Size  Phase Error Step Size
• A phase adjustment of can be expressed in terms of the Reference
clock phase (radians) as:

•  , where is an integer [-3, +4] for 3rd order DDSM

• This corresponds to the case where the VCO signal directly feeds the
variable N-Divider
 DDSM Instantaneous Phase Error
TRef TRef TRef
Reference
Clock
Feedback
Clock

(Nint + yk-1)*TVCO (Nint + yk)*TVCO (Nint + yk+1)*TVCO

• yk = the output from the DDSM on the kth cycle

• The kth cycle starts at a time point = S of all previous periods
DDSM Instantaneous Phase Error
• At the end of the kth cycle:

Eg:
• b[k] = a[k] + b[k-1]
• Now:
• B(z)/A(z) = 1/(1-z-1)

• So:
•

• Note the accumulation / integration

Incorporating DDSM Quantization Noise into the PLL Noise Model
qn,Ref2 vn,PD2/in,PD2 vn,LF 2 qn,VCO2

vtune
qRef + - KPD + HLF(s) + KV/s + qVCO

qfb
• D = N-Div O/P Step Size
+ + 1/N
• In cycles of VCO

• fs = 1/Ts 2
qn,DDSM qn,Div2
• = DDSM sampling rate

( )| |
2 2 2
• m = DDSM order ∆ 1 − 𝑗 𝜔 𝑇 𝑠 2𝑚 2𝜋 1
𝜃 2
𝑛, 𝐷𝐷𝑆𝑀 = ∙ ∙|1 −𝑒 | ∙ ∙
• N = Av (fractional) feedback 12 𝑓 𝑠 𝑁 1 −𝑒
− 𝑗𝜔𝑇 𝑠

division factor
White Quantization DDSM: H(z) Normalization
• w = offset frequency Sampled Phase
Noise over +/- fs/2 BW To Reference Cycle Integration
& Convert to Radians
EE6042 8
DDSM Quantization Step Size
• The DDSM quantization step size in time = 1 VCO Period
• … assuming the VCO directly drives the programmable N-Divider.

• If we wanted to reduce quantization noise by 6dB, we could reduce the period

of the clock driving the N-Divider by ½
•  Run the VCO at 2x the frequency

• Loop dynamics (assuming Ref clock frequency unchanged):

• Average N-Divider value would have to double
• Could preserve loop dynamics by doubling K V => factor KV/N remains unchanged
• (other options exist)