EEC 140B

MOSFTE : Modern Devices

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MOS Scaling

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Short Channel MOS
L~∆L

Current doesn’t saturate

ID ∞ VD2 (See VD >0V)

Space charge limited current

Short Channel MOS

L~∆L

Current doesn’t saturate

ID ∞ VD2 (See VD >0V)

Space charge limited current

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 Short Channel Effect

This is undesirable (i.e. we want to minimize it!)

because circuit designers would like VT to be
invariant with transistor dimensions and biasing
conditions

Scaling Rule of Thumb

•  Lmin minimum gate length for “long channel” behavior
•  Computer simulations, experiments:
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[
Lmin = 0.4 r j xo (Ws + WD ) ]
•  Xo gate oxide thickness (Å)
•  Lmin,Ws,WD,rj(S/D junction depth) in microns

•  S/D junctions, depletion depths (doping), oxide thickness must scale

with minimum gate length

xo
rj L rj
Ws WD

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Short Channel MOSFET Geometry

How much channel charge does the gate control?

Short Channel Effect

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 QB
VT = ψ s + Vi = 2ψ B −
Ci
(QBS − QBL )
ΔVT = VT (short ) − VT (long ) =
Ci

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 Threshold Voltage Shift

•  Threshold Voltage
Q
VT = ψ s + Vi = 2ψ B − B
Ci
(QBS − QBL )
ΔVT = VT (short ) − VT (long ) =
Ci

•  Long Channel transistor:

ZLWmax
QBL = −qNA − qNAWmax
ZL

ZLWmax
QBL = −qNA − qNAWmax
ECE 663
ZL

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 Short Channel transistor: charge in trapezoidal region

⎡ L + L' ⎤
⎢⎣ 2 ⎥⎦ZWmax L + L'
QBS = −qNA = −qNAWmax
ZL 2L

(QBS − QBL ) qN W ⎛ L + L' ⎞

ΔVT = = − A max ⎜1 − ⎟
Ci Ci ⎝ 2L ⎠

Calculations

2
Wmax + (Δ + r j ) = (WD + r j )
rj 2 2
Wmax rj
WD

WD ≈ Wmax

(Δ + r j )2 = (r j + Wmax )2 − Wmax 2
2 2 2 2
Δ2 + r j + 2Δr j = r j + Wmax + 2r jWmax − Wmax

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 Algebra

(Δ + r j )2 = (r j + Wmax )2 − Wmax 2
2 2 2 2
Δ2 + r j + 2Δr j = r j + Wmax + 2r jWmax − Wmax

Δ2 + 2r jΔ− 2r jWmax = 0

2
4r j − 4(2r jWmax ) 2Wmax
Δ = −r j + = −r j + r j 1 +
2 rj

rj
Wmax rj
WD
L − L'
Δ= ⇒
2
L + L' 2L − 2Δ Δ r ⎛ 2Wmax ⎞
= = 1 − = 1 − j ⎜⎜ 1 + − 1⎟⎟
2L 2L L L ⎝ rj ⎠

qNAWmax ⎛ L + L' ⎞ qNAWmax r j

⎜ 1 + 2Wmax − 1⎟
⎛ ⎞
ΔVT = − ⎜1 − ⎟ = − ⎜ ⎟
Ci ⎝ 2L ⎠ Ci L ⎝ rj ⎠

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 Narrow Width Effect
•  Z is comparable to WT

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 Parasitic BJT Action: Punch-Through
L +VD
n-p-n BJT
xo
rj rj
Ws WD

L
++VD
xo S&D depletions touch –
punch through
rj rj
Ws e- WD

Punch Through

•  Electrons can flow from source to drain (no more back to

back junctions) (n-channel enhancement mode)
•  ID α VD2
•  Drain current no longer controlled by gate
•  Transistors won’t “turn off”
•  General “Cure” – high dose implant in sub-gate region to
make narrower depletion widths
•  Higher substrate doping increases parasitic capacitances

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 Oxide Charging
•  Carriers accelerated toward Drain/depletion can have
sufficient energy to escape into the oxide
•  Neutral traps (defects) in the oxide trap charge
•  Leads to long term shift in characteristics in long-
channel
•  Short-channel – more of the gate oxide is near the
drain – big effect – big VT and gm effects - device
failure

N gradient

Lightly Doped Drain Structure

- LDD
Reduced N gradient – smaller electric field near
drain – fewer “hot” electrons into oxide
n to avoid large fields and hot electrons, n+ to
-

get Ohmic contacts (still need to avoid punch-

through)

n-
n+

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 Lightly LDDDoped
from Fujitsu Drain
Structure - LDD
Reduced N gradient – smaller electric
field near drain – fewer “hot” electrons
into oxide
n- to avoid large fields and hot electrons,
n+ to get Ohmic contacts
-n
n+

Velocity Saturation υ ≠ µE

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Velocity Saturation Effect – supressed drain current

∂ID
g m−sat ≡ = ZCi υsat = const.
∂VG sat

Measurement Calculation w/ Calculation w/o

Velocity Saturation Velocity Saturation

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HEMT

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