DECLARATION

AND
INSTANTIATION
Prepared by: Engr. France Mae D. Camogao
MODULE
• Is the basic building blocks of Verilog.
• A module can be an element or a collection of lower-level design blocks.
• It provides the require functionality to the higher-level block through its port
interface but hides the internal implementation
• It provides the flexibility to the designer to modify the module internals without
affecting the rest of the design.
VERILOG
FRAMEWOR
K
MODULE
INSTANTIATI
ON
•
•
Instantiation allows the creation of hierarchy in Verilog description
It is a process of creating object from a module template. Objects are called
instances.
• In Verilog, nesting of module is illegal.
• One module definition cannot contain another module definition.
• We can incorporate the copies of other module by instantiating them.
Example: 4*1 MUX using 2*1 MUX
Example: 4*1 MUX using 2*1 MUX
VERILOG
KEYWORDS
•
•
Case sensitive.
$, underscore, alphanumeric can be used.
 Comments
• Comments are basically used for documentation. It also improves the readability of the code.

There are two ways to write the comment:

• Single-line comment – It starts with “//”. Verilog skips from that point to the end of the line.
• Multiple-line comment – It starts with “/*” and ends with “*/”. Multiple-line comment cannot
be nested.
Simulation, Synthesis
and Design methodology
in Verilog
Prepared by: Engr. France Mae D. Camogao
SIMULATION
• Simulation is used to verify the functionality of the digital design that is
modeled using HDL like Verilog.
• For simulation purpose we apply different input stimulus to the design at
different time, to check whether the RTL code behaves in intended way or not.
SYNTHESIS
• Synthesis is the process of transforming your HDL design into a gate-level
netlist, given all the specified constraints and optimization settings.
• Logic synthesis is the process of translating and mapping RTL code written in
HDL (such as Verilog or VHDL ) into technology specific gate level
representation.
SYNTHESIS
There are 3 steps in Synthesis:
• Translation: RTL code is translated to technolohgy independent
representation. The converted logic is available in boolean equation form.
• Optimization: Boolean equation is optimized using SoP or PoS optimization
methods.
• Technology mapping: Technology independent boolean logic equations are
mapped to technology dependant library logic gates based on design
constraints, library of available technology gates. This produces optimized
gate level representation which is generally represented in Verilog.
SYNTHESIS
Design Methodology
• Top-down design methodology
• Bottom-up design methodology
Design Methodology
• Top-down design methodology
• Bottom-up design methodology
Top-down design methodology
• We first define the top level block and identify the sub-blocks necessary to
build the top level block
• These sub-blocks are further subdivided until we come to leaf-cells, which
cannot be further divided
Top-down design methodology
Bottom-up design
methodology
• We first identify the building blocks that are available to us
• By using these building blocks, we build the bigger blocks
• Theses are then used for higher-level blocks until we build the top-level block
in design
Bottom-up design
methodology
DATA TYPES IN VERILOG
Prepared by: Engr. France Mae D. Camogao
DATA TYPE
• Data type is a classification that specifies which type of value can be assigned
to a variable.
• What type of mathematical operation can be applied to the data type.

TWO DATA TYPES IN VERILOG

• Register
• Nets
Register Data Type
• reg (most widely used)
• integer (used for loop counting)
• real (used to store floating point numbers)
• time (keeps track of simulation time)
Register Data Type
• Register represents data storage elements
• It is a variable that can hold a value
• It is commonly declared by the keyword “reg”
• The default value of reg data type is “X”
• Register represents a class of data types such as reg, integer, real, time etc.
 Register Data Type
reg reset;
• reg count;
initial
//single bit register variable
begin
reset = 1’b0;
• reg [7:0] bus;
#10 reset = 1’b1;
//8 bit bus
#10 reset = 1’b0;
end
Integer Data Type
(REGISTER)
• An integer is a general purpose register data type
• Declared by the keyword “integer”
• Store the values as signed quantities eg. 0,4,-17,-148 etc
• Generally used for counting purpose
• Default value is X
• Default width is 32bits
integer count, new_num;
initial
begin
count = 4;
new_num = -17;
end
Real Data Type
(REGISTER)
• Declared by the keyword “real”
• Allows decimal and scientific notation eg. 0.3, 4.63, - 17.5 etc
• Not synthesizable
• Default value is 0.0
• Rounded off to the nearest integer when it is assigned to an integer
real count, new_num; integer a;
initial real b;
begin initial
count = 4.76; begin
new_num = -1.3; b= -6.5;
end a = b;
end
// a will be assigned the -7
Time Data Type
(REGISTER)
• A special time register data type is used to store the simulation time
• Declared by the keyword “time”
• Time variables are unsigned in nature
• Width is implementation-specific but is at least 64 bits
• Not synthesizable (useful for testbench)
• Default value is X
time new_sim_time;
initial
begin
new_sim_time = $time;
// save the current simulation time

end
Net Data Type
• Nets represent connections between hardware elements.
• It must be continuously driven i.e. cannot be used to store the values.
• Nets are declared primarily with the keyword “wire”
• The default value of net is Z
• Net represents a class of data types such as wire, wand, wor, tri, triand, trior,
trireg etc.
 Net Data Type
• Consider the below figure, Net c is connected to the output of AND Gate.

a module half_add (a,b,sum,carry);

c input a,b;
b output sum, carry;

assign sum = a ^ b;
assign carry = a & b;
a sum
Half adder endmodule

b carry
Numbers
Syntax: <size>’<base><number>
• 1’b1 logic – 1 (1-bit)
• 8’h21 8 bit number 0010 0001
• 12’ha35 12 bit number 1010 0011 0101
• 12’o42xx 12 bit number 100 010 xxx xxx
• 4’d1 4 bit number 0001
• 35 signed number, in 32 bits
 Numbers
• BINARY - B or B
• OCTAL - o or O
• DECIMAL – d or D
• HEXADECIMAL – h or H
Use underscore to improve readability.
32’h64_ab can also be written as
32’b 0110_0100_1010_1011

ZERO, X and extension

4’bX0 xxxx_0
5’d1 0000_1
16’hz6 zzzz_zzzz_zzzz_0110
Values and Signal
strength
Verilog supports 4 values levels and 8 strength levels to model the
functionality of real hardware.
Values and Signal
strength
Verilog supports 4 values levels and 8 strength levels to model the
functionality of real hardware.
PORT
ASSIGNMENT
Input, Output, & Inouts
• Input - internally net, externally reg or net
• Output – internally reg or net, externally net
• Inout – only wire data type
input
module

Reg or net net

input
output
module

Reg or net net

output
inout
module

net net

inout