D.

Jaswanth Sai - 9920005090

Implement a PnR Flow at N. Sravan Kumar Naidu

Ch. Jogeswara Rao
- 9920005065
- 9920005211

the Block Level to Achieve K. Naveen Kumar - 9920005216

the Highest Utilization Rate Guided by

Dr. K. Pandiaraj
Professor,
Department of Electronics and Communication Engineering,
School of Electrical, Electronics and Biomedical Technology,
© Kalasalingam academy of research and education Kalasalingam Academy of Research and Education
 Contents
 Introduction
 literature survey
 Abstract
 Problem statement
 Objective
 Scope
 References

© Kalasalingam academy of research and education KARE - CSP REVIEW

 Introduction
 PNR flow, or placement and routing flow, is a series of steps that are used to place and route the components
of an integrated circuit (IC).
 The goal of PNR flow is to maximize the utilization of the chip area while also meeting the design
constraints, such as timing and power consumption.
 The PNR flow can be implemented at the block level or at the top level. The block-level PNR flow is
typically used for large and complex ICs, where it is necessary to optimize the placement and routing of
individual blocks.
 The top-level PNR flow is typically used for smaller and less complex ICs, where it is possible to optimize
the placement and routing of the entire chip at once.

© Kalasalingam academy of research and education

 Introduction (Cont.)
 To achieve the highest utilization rate, the PNR flow should be carefully designed and implemented. The
following are some of the factors that should be considered:
 The size and shape of the block: The block should be sized and shaped to maximize the utilization of the
chip area.
 The placement of the blocks: The blocks should be placed in a way that minimizes the routing congestion.
 The routing of the nets: The nets should be routed in a way that minimizes the wire length and maximizes
the signal integrity.
 The design constraints: The PNR flow should be designed to meet the design constraints, such as timing
and power consumption.

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 Literature Survey
S. Title Methodology Year Qualitative Analysis Limitations
No
1. PNR flow methodology for Two placement strategies IEEE, 1. A 16% improvement in the overall on- 1. The timing analysis is done only on
congestion optimization using have been considered – 2021 chip delay. the LLC module of the DDR
different macro placement peripheral and donut, for the subsystem.
2. A 19.6% power reduction is observed
strategies of DDR memories LLC module.
in the peripheral macro placement 2. Limited corners were used to optimize
A congestion-optimized, strategy as compared to island macro the setup and hold timing paths. Only
floor-plan to Place and placement. 10 extreme corners were used to
Route (PNR) flow perform design closure.
3. The overall congestion for peripheral
methodology has been
macro placement is 0.32%,
presented for each of these
placement strategies using
Cadence Innovus
Implementation System and
Synopsis IC Compiler II.

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 S. Title Methodology Year Qualitative Analysis Limitations
No
2. BLOCK LEVEL TIMING AND POWER The physical design is performed A DISSERTATION 1. Implemented default place and 1. Cannot identify all the non-critical timing
OPTIMIZATION OF VLSI PHYSICAL in two levels, PNR Flow and ECO REPORT route flow on power gated paths.
DESIGN Flow. design block. Performed
2. optimizing only those paths by swapping
multiple trials on design blocks
HVT cells.
to optimize the design for lower
power consumption and select
the best method among them.

2. Studied the default design for

power implementation and
adopted it in a suitable manner
to further obtain better leakage
power optimization.

3. leakage power per area(mm2)

is reduced by 45% and area
also reduced by 10 %

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 S. Title Methodology Year Qualitative Analysis Limitations
No
MDPI, 2021
3. A Novel Standard-Cell-Based 1. Operational 1. The SG-DIGOTA results area is The operation of Digital OTAs is typically strongly
Implementation of the Digital OTA Transconductance Amplifier very competitive in the small sensitive to PVT variations and mismatch and
Suitable for Automatic Place and Route (OTA) signal domain, especially often requires suitable calibration strategies to
considering the very small achieve high production yield.
2. A commercial 130 nm CMOS
silicon area required while
process by using an
performing less in the large
automatic place and route
signal domain.
flow for layout generation
starting from the Verilog
netlist.

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 S. Title Methodology Year Qualitative Analysis Limitations
No
MDPI, 2023
4. A High Performance 0.3 V Standard- 1. An ultra-low voltage (ULV) 1. Simulation results have shown a Power consumption of the proposed OTA is
Cell-Based OTA Suitable for Automatic standard cell-based OTA. differential gain of 50 dB with a relatively high
Layout Flow gain–bandwidth product of 10
MHz when driving a 150 pF load
capacitance.

2. Good robustness is achieved

under PVT variations, in
particular for voltage gain, offset
voltage, and phase margin.
State-of-the-art small signal
figures of merit and limited area
footprint are key characteristics
of the proposed amplifier

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 Abstract
 The implementation of a Physical-to-Layout (PNR) flow at the block level in integrated circuit (IC) design
is a strategic approach aimed at optimizing chip utilization and overall performance. This process involves
translating the logical design representation into a physically efficient layout that maximizes resource
utilization while meeting design constraints. The primary objectives encompass achieving high utilization
rates, optimizing performance, ensuring efficient area usage, enhancing power efficiency, and achieving
design closure. By closely integrating floor planning, placement, clock tree synthesis, and routing, this PNR
approach results in compact designs that exhibit predictable performance under manufacturing constraints.
Through this method, IC designs can realize their full potential by seamlessly combining logical design
intent with physical realities to attain optimal utilization and performance.

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 Problem Statement
• To achieve the highest utilization rate is to find a placement and routing solution that maximizes the
amount of silicon area that is used by the design, while still meeting the design rules and timing
requirements.

© Kalasalingam academy of research and education KARE - CSP REVIEW

 Objective
• To achieve the highest utilization rate, maximize the amount of silicon area that is used by the design.
• To minimize the amount of empty space between placing and routing blocks.
• To implement a block-level design with specifications as follows:
40nm Technology, using 34 Macros and 38k Standard Cells, a Clock Frequency of 1G Hz, a Supply voltage of 1.1V, 7
Metal Layers, a Max IR drop of 5% of supply voltage, and a Power budget of 600mW.

© Kalasalingam academy of research and education KARE -CSP REVIEW

 Scope

The scope of implementing a PNR flow at the block level to achieve the highest utilization rate is to
create a PNR flow that is efficient and effective in meeting the needs of the block. This includes ensuring
that the PNR flow is:
• Responsive to the needs of residents: The PNR flow should be designed to meet the needs of the
residents of the block, such as providing transportation options, access to essential services, and
opportunities for recreation.
• Efficient in terms of resources: The PNR flow should be designed to use resources efficiently, such as by
minimizing the use of transportation and energy.
• Effective in achieving its goals: The PNR flow should be designed to achieve its goals, such as reducing
traffic congestion, improving air quality, and increasing access to opportunities.

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 References
1. J. Fadnavis, Kariyappa B.S, “PNR flow methodology for congestion optimization using different macro
placement strategies of DDR memories ”, International Journal of Advanced Technology and Engineering
Exploration, Vol 8(80) July 2021.
2. Sandeep Kumar Gupta, “Block Level Timing And Power Optimization Of Vlsi Physical Design ”, A Dissertation
Report, Electronics & Communication Engineering Delhi Technological University, May 2022.
3. Palumbo, G., Scotti, G.,“A Novel Standard-Cell-Based Implementation of the Digital OTA Suitable for Automatic
Place and Route” MDPI October 2021.
4. Della Sala, R.; Centurelli, F.; Scotti, G. A High Performance 0.3 V Standard-Cell-Based OTA Suitable for
Automatic Layout Flow. MDPI April 2023.

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