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VHDL 360 2
Course Prerequisites
Digital/Logic design System architecture Computer architecture (is a plus) Software programming (is a plus)
VHDL 360
Module 0
Introduction to VHDL
Objective
Overview on VHDL Skills gained:
VHDL History and usage VHDL design flow Understand concurrency
VHDL 360
What is VHDL?
VHDL is
A High level modeling language A model that will be either used to synthesize H/W or just used as a simulation model
Only a subset of the language can be used for synthesis
VHDL Standard
Synthesizable VHDL
VHDL 360
VHDL history
Very high speed integrated circuit Hardware Description Language
Early 1980s: Developed by U.S. Department of Defense 1987: IEEE Standard 1076 - 87 1993: IEEE Standard 1076 93 (New features) 1999: Analog Mixed Signal extension (VHDL-AMS) 2008: IEEE Std 1076 2008 (New features)
VHDL 360
Uses of VHDL
Design representation
using different abstraction levels
VHDL 360
failed Succeeded
Synthesis
Start Production
Post Synthesis Simulation failed
Lets have a quick look at the following model & try to understand the main sections in the code
-LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY model1 IS PORT( a : IN std_logic; b : IN std_logic; c : IN std_logic; d : IN std_logic; e : OUT std_logic ); END model1 ; ARCHITECTURE rtl OF model1 IS -- This is a comment SIGNAL x : std_logic; SIGNAL y : std_logic; BEGIN -- This is another comment x <= a AND b; y <= c AND d; e <= x OR y; END rtl; -- end of line comment
Functional/behavioral Implementation
VHDL 360
10
-LIBRARY ieee;
ENTITY model1 IS PORT( a : IN std_logic; b : IN std_logic; c : IN std_logic; d : IN std_logic; e : OUT std_logic ); END model1 ;
Defining a model with name model1 Defining the interface ports, their types & their direction
model1
VHDL 360 11
VHDL 360
12
Concurrency
Think Hardware: In real life, the value @ x is always the result of a AND b, whenever a/b changes x will change accordingly Similarly the value @ y will always change whenever c/d changes It might happen that the value @ x changes at the same time the value @ y changes Both changes happen concurrently
BEGIN x <= a AND b; y <= c AND d; e <= x OR y; END rtl;
These assignment statements are concurrent, they can be written in any order
VHDL 360
13
VHDL 360
14
VHDL 360
15
VHDL 360
16