Professional Documents
Culture Documents
Text Book: HDL Programming VHDL and Verilog by Nazeih M Botros, 2009 reprint,
Dreamtech press
Behavioral Description Highlights
Referring to the VHDL code, the entity half_add has two input
ports, I1 and I2, and two output ports, O1 and O2.
The ports are of type bit; this type is recognized by the VHDL
package without the need to attach a library.
This is not the case when a signal appears on both the right-
hand side of the statement and the left-hand side of another
statement, which will be seen later
.
Structure of the HDL Behavioral Description
Event on I1
activates
ALWAYS
I1 10 ns
1
I22
Execution of signal-assignment statements
Verilog Description
module half_add (I1, I2, O1, O2);
input I1, I2;
output O1, O2;
reg O1, O2;
/* Since O1 and O2 are outputs and they are written inside “always,”
they should be declared as reg */
always @(I1, I2)
begin
#10 O1 = I1 ^ I2; // statement 1.
#10 O2 = I1 & I2; // statement 2
/*The above two statements are signal-assignment statements with 10 simulation
screen units delay*/
/*Other behavioral (sequential) statements can be added here*/
end
endmodule
The VHDL Variable-Assignment Statement
Varb: process(t1)
variable temp1, temp2: bit; begin
st3: temp1: = t1;
st4: temp2: = not temp1; st5: S1 <= temp1;
st6: S2 <= temp2; end process;
Assignment operator
• For statements st5 and st6, S1 acquires the value of temp1 (1) at
T1 + D, and S2 acquires the value of temp2 (0) at T1 + D.
For statements st5 and st6, S1 acquires the value of temp1 (1) at T1
+ D, and S2 acquires the value of temp2 (0) at T1 + D. Because D is
infinitesimally small, S1 and S2 appear on the simulation screen as if
they acquire their new values at T1
Sequential Statements
IF Statement
IF is a sequential statement that appears inside process in VHDL or
inside always or initial in Verilog. It has several formats, some of which
are as follows
Execution of IF as ELSE-IF
Verilog
if (Boolean Expression1)
begin
statement1; statement 2;.....
end
else if (Boolean expression2)
begin
statementi; statementii;.....
end
else
begin
statementa; statement b;....
end
Implementing ELSE-IF
Implementing ELSE-IF
if (signal1 == 1’b1)
temp = s1;
else if (signal2 == 1’b1)
temp = s2;
else
temp = s3;
D-Latch
If, for example, test value1 is true (i.e., it is equal to the value of the
control expression), statements1 is executed.
The case statement must include all possible conditions (values) of the
control-expression.
The case statement can be used to describe data listed into tables
Positive Edge-Triggered JK Flip-Flop Using the case
Statement
module JK_FF (JK, clk, q, qb);
input [1:0] JK;
input clk;
output q, qb;
reg q, qb;
always @ (posedge clk)
begin
case (JK)
2’d0 : q = q;
2’d1 : q = 0;
2’d2 : q = 1;
2’d3 : q =~ q;
endcase
qb =~ q;
end
endmodule
The wait-for Statement
module waitstatement(a,b,c);
output a,b,c;
reg a,b,c;
initial begin
// Initialize Inputs a = 0;
b = 0;
c = 0;
end
always
begin
#10 ;
a = ~ a;
end
always
begin
#20 ;
b = ~ b;
end
always
begin
#40 ;
c = ~ c;
end
endmodule
The wait-for Statement
Verilog For-Loop
for (i = 0; i <= 2; i = i + 1)
begin
if (temp[i] == 1’b1) begin
result = result + 2**i;
end
end
statement1; statement2; ....
While-Loop
Verilog While-Loop
while (i < x)
begin
i = i + 1;
z = i * z;
end
In the above example, the condition is (i < x). As long as i is less than x, i is
incremented, and the product i * z (i multiplied by z) is calculated and
assigned to z.
Verilog repeat
Verilog repeat
In Verilog, the sequential statement repeat causes the execution of
statements between its begin and end to be repeated a fixed number of
times; no condition is allowed in repeat.
Verilog forever
The statement forever in Verilog repeats the loop endlessly. One common
use for forever is to generate clocks in code-oriented test benches. The
following code describes a clock with a period of 20 screen time units:
initial begin
Clk = 1’b0;
forever #20 clk = ~clk;
Verilog code describes a four-bit binary counter
• Verilog recognizes all the primitive gates such as AND, OR, XOR, NOT, and
XNOR gates. Basic VHDL packages do not recognize any gates un- less the
package is linked to one or more libraries, packages, or modules that have
the gate description. Usually, the user develops these links, as will be done
in this chapter.
HDL code that describes a half adder under the name of system using
structural description. The entity (VHDL) or module (Verilog) name is system;
there are two inputs, a and b, and two outputs, sum and cout.
In the VHDL description, the structural code (inside the architecture) has two
parts: declaration and instantiation.
component xor2
• To specify the type of the component (e.g., AND, OR, XOR, etc.), additional
information should be given. If the system has two or more identical
components, only one declaration is needed.
• The instantiation part of the code maps the generic inputs/outputs to the
actual inputs/outputs of the system. For example, the statement
Organization of Structural Description
maps input a to input I1 of xor2, input b to input I2 of xor2, and output sum
to output O1 of xor2.
This mapping means that the logic relationship between a, b, and sum is the
same as between I1, I2, and O1.
Note that the mapping of S is written before writing the mapping of the
inputs; we could have used any other order of mapping.
This means that their execution depends on events, not on the order in which
the statements are placed in the module.
So, placing statement A1 before statement X1 does not change the outcome
of the VHDL program
Organization of Structural Description
Note that the mapping of S is written before writing the mapping of the
inputs; we could have used any other order of mapping.
This means that their execution depends on events, not on the order in which
the statements are placed in the module.
So, placing statement A1 before statement X1 does not change the outcome
of the VHDL program
Organization of Structural Description
Verilog has a large number of built-in gates. For example, the statement:
xor X1 (sum, a, b);
The inputs are a and b, and the output is sum. X1 is an optional identifier for
the gate; the identifier can be omitted as:
Verilog Description