Advanced Digital Electronics Laboratory Exp.

8
Experiment 8
Sequential Code1:
Design Example 2-digit counter
Learning Objectives:
1. Some fundamental VHDL Sequential statement will introduced in this experiment, with
special emphasis on those that are synthesizable.
2. To design, synthesize, and simulate the operation of a counter circuit with VHDL language.
Equipment and Materials:
full version of Xilinx ISE 9.2i software installed on your laboratory personal computer.
Introduction:
VHDL code is inherently concurrent. PROCESSES, FUNCTIONS, and PROCEDURES are the
only sections of code that are executed sequentially. One important aspect of sequential code
is that it is not limited to sequential logic. Indeed, with it we can build sequential circuits as
well as combinational circuits. Sequential code is also called behavioral code. The statements
discussed in this section are all sequential, that is, allowed only inside PROCESSES,
FUNCTIONS, or PROCEDURES. They are: IF, WAIT, CASE, and LOOP.
VARIABLES are also restricted to be used in sequential code only (that is, inside a PROCESS,
FUNCTION, or PROCEDURE). Thus, contrary to a SIGNAL, a VARIABLE can never be global, so
its value cannot be passed out directly.
1. PROCESS: it syntax is shown below

Example:
PROCESS (a, b, cin)
BEGIN
s <= a XOR b XOR cin;
cout := (a AND b) OR (a AND cin) OR (b AND cin);
END PROCESS;
2. IF: The syntax of IF is shown below

Example:
IF (x<y) THEN temp:="11111111";
ELSIF (x=y AND w='0') THEN temp:="11110000";
ELSE temp:=(OTHERS =>'0');
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3. WAIT: Its syntax (there are three forms of WAIT) is shown below

Example:
PROCESS
BEGIN
WAIT UNTIL (clk'EVENT AND clk='1');
IF (rst='1') THEN output <= "00000000";
ELSIF (clk'EVENT AND clk='1') THEN output <= input;
END IF;
END PROCESS;
4. CASE: Its syntax is shown below

Example:
CASE control IS
WHEN "00" => x<=a; y<=b;
WHEN "01" => x<=b; y<=c;
WHEN OTHERS => x<="0000"; y<="ZZZZ";
END CASE;
5. LOOP: There are several ways of using LOOP, as shown in the syntaxes below.
FOR / LOOP: The loop is repeated a fixed number of times.

Example:
FOR i IN 0 TO 5 LOOP
x(i) <= enable AND w(i+2);
y(0, i) <= w(i);
END LOOP;
WHILE / LOOP: The loop is repeated until a condition no longer holds.

Example:
--In this example, LOOP will keep repeating while i < 10.
WHILE (i < 10) LOOP
WAIT UNTIL clk'EVENT AND clk='1';
(other statements)
END LOOP;
EXIT: Used for ending the loop.
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Example:
FOR i IN data' RANGE LOOP
CASE data(i) IS
WHEN '0' => count:=count+1;
WHEN OTHERS => EXIT;
END CASE;
END LOOP;
NEXT: Used for skipping loop steps.

Example:
FOR i IN 0 TO 15 LOOP
NEXT WHEN i=skip; -- jumps to next iteration
(...)
END LOOP;
Procedures:
1.Write a VHDL sequential code to implements a progressive 2-digit
decimal counter (0→99→0), with external asynchronous reset as
shown in figure.
2.Implement your designed in step 1 using Xilinx ISE 9.2i tools for Spartan
3E FPGA board. Follow the same steps in previous in Experiments to
synthesize and obtain a timing diagram after simulation to verify
correct outputs.
3. Record your results (VHDL code, RTL, Timing diagram)
Report :
1.List all sequential statements used in VHDL code of procedure 1.
2.How does a synchronous counter differ from an asynchronous counter?
3.How you can download your design using Spartan 3E FPGA board?
4.Complete the VHDL code of your counter if SSD (seven-segment display) circuit is to be added
to the design as shown below( use also sequential statements):

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