Latch-up in CMOS circuits

Latch-Up problem is inherent in the p-well and n-

well process is due to the relatively large no.of junctions.

These junctions formed the consequent presence

of parasitic transistors and diodes.

The parasitic components give rise the establishment

of low conducting path between VDD and VSS with disastr-
ous results.

Latch-Up may be induced by glitches on the supply

rails or by incident radiation.
VDD VSS

Latch-Up effect in n-well process

 Fig shows the key parasitic components associated
with n-well structure in which an inverter circuit has
been formed.

Two transistors and two resistances which form a

path between VDD and VSS.

If sufficient substrate current flows to generate

enough voltage across RS to turn on transistor Q2, this
will then draw current through Rn.
 If the voltage developed is sufficient, Q1 will also
turn on , establishing a self sustaining low resistance
path between the supply rails.

If the current gains of the two transistors are such

that β1 x β2 >1, latch-up may occur.
 Remedies for the problem include

1.an increase in substrate doping levels with a

consequent drop in the value of Rs

2. reducing Rn by control of fabrication parameters

and by ensuring a low contact resistance to VSS.

3. other more elaborate measures such as the

introduction of guard rings.