ARM – THUMB MODE

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AGENDA
1. Thumb mode
2. Difference between Thumb and Normal mode
3. Switching to Thumb Mode

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THUMB MODE - INTRODUCTION

Jazelle state is not set and so is THUMB state since T=0. And hence the state selected is
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ARM. And the mode value is set as 11111.
THUMB MODE -
INTRODUCTION
oCore has two execution states ARM and Thumb;
oThumb is a compressed and 16 bit representation of a subset of the ARM instruction
set.
oLike ARM, Thumb also uses load store architecture for data processing, data
transfer and control flow instructions.
oThe standard chip that includes the Thumb instruction set is the ARM7TDMI where
"T" specifies Thumb.

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THUMB MODE

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DIFFERENCE

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 REGISTER SET

When operating in the 16-bit Thumb state, the application encounters a slightly
different set of registers. Figure 1 compares the programmer's model in that
state to the same model in the 32-bit ARM state.

Figure 1 ARM vs. Thumb programmer's

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REGISTERS

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 HOW TO SET THUMB STATE?
D3 is the default value for the CPSR as shown in the below. So by default one can observe that the
Thumb state is disabled. To get it enabled, as already discussed CPSR should be accessed and T bit
should be set.

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 CONTD.,
Setting the T bit can be done by adding 0x20 to the D3. It will then set the T bit and
eventually the THUMB mode will be set

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MOV AND SHIFT – 3-ADDRESS

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ADD/SUB – 3-ADDRESS

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MOV/ADD/CMP/SUB #IMM – 2-
ADDRESS

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OTHER ALU OPERATIONS – 2-
ADDRESS

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USING HI-REGISTERS / BX

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LOAD 1 – PC-RELATIVE

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LDR/STR WITH REGISTER
OFFSET

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LDR/STR -3 : SIGNED
BYTE/HALF-WORD

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LDR/STR-4 – IMMEDIATE
OFFSET

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LDR/STR-5 – HALF-WORD

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LDR/STR-5 : SP-RELATIVE

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BRANCH INSTRUCTION FORMATS
FEATURES

•Different format for each case

•Offset is reduced to 11bit and 8 bit
•Offset is shifted left by 1-bit (to give half-word alignment) and sign-extended to 32 bits.
•BL is more subtle to give 22-bit offset using link register for temporary storage
•No direct mapping to ARM instructions as Thumb require half-word aligned offsets.
 BL INSTRUCTION

To allow for a reasonably large offset to the target subroutine each of these two
instructions is automatically translated by the assembler into a sequence of two 16
bit thumb instructions
1. H = 10
LR := PC + (sign-extended offset shifted left 12 places);

2. H = 11
PC := LR + (offset shifted left 1 place)

3. LR := address of next instruction

SOFTWARE INTERRUPT INSTRUCTION

1 1 0 1 1 1 1 1 8 – Bit Immediate

•Address of next instruction is saved in r14_svc

•CPSR is saved in r14_svc
•Disables IRQ, Clears T bit, Enters Supervisor mode
•PC is forced to 0x08
•8 bit immediate is zero extended to fill the 24-bit field in the ARM instruction.
•Limits SWIs to first 256 of 16 million ARM SWIs.
 THUMB-ARM DECOMPRESSION

•Translation from 16-bit Thumb instruction to 32-bit ARM instruction

•Condition bits changed to ‘always’
•Lookup to translate major and minor opcodes
•Zero extending 3-bit register specifiers to give 4-bit specifiers
•Zero extending immediate values
•Implicit ‘S’(affecting condition codes) should be explicitly specified.
•Thumb 2-address format must be mapped to ARM 3-address format
PROPERTIES

•Thumb code requires 70% of space of ARM code

•Thumb code uses 40% more instructions than the ARM code
•With 32-bit memory ARM code is 40% faster
•With 16-bit memory Thumb code is 45% faster than ARM code
•Thumb code uses 30% less external memory power than ARM code.

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