AMBA BUS

Dept. of CSE
ASE-CBE
 BUS
Bus is the mechanism by which CPU
communicates with memory and IO devices.
It is not just a collection of wires. In fact, bus
defines the protocol for communication.
Bus defines the corresponding transport
mechanism between the CPU and memory and
IO devices.
 BUS
Bus - a shared communication link, because
there are many devices which can actually sit on
the bus.
A single set of wires - used to connect multiple
subsystems.
Bus is also fundamental tool for composing large
and complex systems
What defines Bus
Transaction Protocol

Timing and Signaling

Specification

Bunch of Wires

Electrical Specifications

Physical mechanical
characteristics - Connectors
 Generic Bus Structure
Address Bus:

Data Bus:

Control Bus:

Status Bus:
 Bus Characteristics
Bus signals are usually tri stated
Tristate : Low State
High State
Tri-State ( High impedance state –
electrically isolated but physically connected)
So, if a device would like to disconnect itself from
the bus, it would drive its interface lines to tri
state high impedance state. So, effectively it gets
disconnected from the bus. So, all these devices
are really sharing the common set of signal lines.
 Bus Characteristics
• Address and Data lines may be multiplexed.
• Every device on the bus must be able to drive
the maximum bus load. Because maximum
bus load would determine what are the
maximum number of device that you can
actually put on the bus.
• Bus may include a clock signal. Timing is
relative to clock.
What is the major difference between Control lines
and Signal lines ???
Control Signal === CPU  Peripherals
Status Signal === Peripherals  CPU

Can we club together Address and Data lines ?

Hint: AD0-AD7
Additional line needed ALE
Adv: Instead of 16 (A0-A7 and D0-D7) pins or lines we
need only 8+1 (AD0-AD7 and ALE)

Also recall about parallel and serial Communication

Hard Disk : P ATA and S ATA cables
Asynchronous Communication Protocol:
Example : UART – Universal Asynchronous
Receiver Cum Transmitter
No Common Clock and so Framing is Required

Start D0 D1 D2 D3 D4 D5 D6 D7 STOP
Synchronous Communication Protocol (Common Clock)
Example: I2C

SPI –Serial Peripheral Interface

ARM Bus
Basic ARM Memory System
DRAM Memory Organisation
DRAM Memory Organisation
 AMBA
Advanced Microcontroller Bus
Architecture
ARM processor cores have bus interfaces that
are optimized for high-speed cache interfacing.
Where a core is used, with or without a cache,
as a component on a complex system chip, some
interfacing is required to allow the ARM to
communicate with other on-chip macrocells.

ARM Limited specified the Advanced

Microcontroller Bus Architecture, AMBA, to
standardize the on-chip connection of different
macrocells.
Three buses are defined in AMBA Specification:
• The Advanced High-performance Bus (AHB)
• The Advanced System Bus (ASB)
• The Advanced Peripheral Bus (APB)
• AHB is used to connect high-performance
system modules. It supports burst mode data
transfers and split transactions, and all timing
is reference to a single clock edge.
• ASB is used to connect high-performance
system modules. It supports burst mode data
transfers.
• APB offers a simpler interface for low-
performance peripherals.
• A typical AMBA-based microcontroller will
incorporate either an AHB or an ASB together
with an APB as illustrated in Figure The ASB is
the older form of system bus, with AHB being
introduced later to improve support for higher
performance, synthesis and timing
Verification.
• The APB is generally used as a local secondary
bus which appears as a single slave module on
the AHB or ASB.
Typical AMBA based systems
AMBA AHB

AHB is a new generation of AMBA bus which is intended to address the

requirements of high-performance synthesizable designs. It is a high-
performance system bus that supports multiple bus masters and provides high-
bandwidth operation.

An AMBA AHB design may contain one or more bus masters. However, it
would also be common for a Direct Memory Access (DMA) or Digital Signal
Processor (DSP) to be included as bus masters.

The external memory interface, APB bridge and any internal memory are the
most common AHB slaves. Any other peripheral in the system could also be
included as an AHB slave. However, low-bandwidth peripherals typically reside
on the APB.
A typical AMBA AHB system design contains the following components:

AHB master:
A bus master is able to initiate read and write operations by providing an address
and control information. Only one bus master is allowed to actively use the bus at
any one time.
AHB slave:
A bus slave responds to a read or write operation within a given address-space
range. The bus slave signals back to the active master the success, failure or
waiting of the data transfer.
AHB arbiter:
The bus arbiter ensures that only one bus master at a time is allowed to initiate
data transfers. Even though the arbitration protocol is fixed, any arbitration
algorithm, such as highest priority or fair access can be implemented depending on
the application requirements.
An AHB would include only one arbiter, although this would be trivial in single
bus master systems.
AHB decoder:
The AHB decoder is used to decode the address of each transfer and provide a
select signal for the slave that is involved in the transfer.
A single centralized decoder is required in all AHB implementations.
AMBA ASB

ASB is the first generation of AMBA system bus. ASB sits above the current APB and
implements the features required for high-performance systems including:

• burst transfers
• pipelined transfer operation
• multiple bus master

A typical AMBA ASB system may contain one or more bus masters. However, it would also
be common for a Direct Memory Access (DMA) or Digital Signal Processor (DSP) to be
included as bus masters.
ASB master:
A bus master is able to initiate read and write operations by providing an address
and control information. Only one bus master is allowed to actively use the bus at
any one time.
ASB slave:
A bus slave responds to a read or write operation within a given address-space
range. The bus slave signals back to the active master the success, failure or
waiting of the data transfer.
ASB decoder:
The bus decoder performs the decoding of the transfer addresses and selects
slaves appropriately. The bus decoder also ensures that the bus remains operational
when no bus transfers are required. A single centralized decoder is required in all ASB
implementations.
ASB arbiter:
The bus arbiter ensures that only one bus master at a time is allowed to initiate
data transfers. Even though the arbitration protocol is fixed, any arbitration
algorithm, such as highest priority or fair access can be implemented depending on
the application requirements.

An ASB would include only one arbiter, although this would be trivial in single bus master
systems.
AMBA APB

The APB is part of the AMBA hierarchy of buses and is optimized for minimal power
consumption and reduced interface complexity.

The AMBA APB appears as a local secondary bus that is encapsulated as a single AHB
or ASB slave device. APB provides a low-power extension to the system bus which
builds on AHB or ASB signals directly.

The APB bridge appears as a slave module which handles the bus handshake and
control signal retiming on behalf of the local peripheral bus.

The AMBA APB should be used to interface to any peripherals which are low
bandwidth and do not require the high performance of a pipelined bus interface.

An AMBA APB implementation typically contains a single APB bridge which is

required to convert AHB or ASB transfers into a suitable format for the slave devices
on the APB. The bridge provides latching of all address, data and control signals, as
well as providing a second level of decoding to generate slave select signals for the APB
peripherals.

All other modules on the APB are APB slaves.

 Bus Arbitration

A bus transaction is initiated by a bus master which requests

access from a central arbiter.
The arbiter decides priorities when there are conflicting
requests, and its design is a system specific issue.
The ASB only specifies the protocol which must be followed:
The master, x, issues a request (AREQx) to the central
arbiter.
When the bus is available, the arbiter issues a grant (AGNTx)
to the master.
(The arbitration must take account of the bus lock signal
(BLOK) to ensure that atomic bus transactions are not
violated.)
 Bus Transfer

• When a master has been granted access to the

bus, it issues address and control information to
indicate the type of the transfer and the slave
device which should respond. The following
signal is used to define the transaction timing:
• The bus clock, BCLK. This will usually be the
same as mclk, the ARM processor clock.
• The bus master which holds the grant then
proceeds with the bus transaction using the
following signals:
• Bus transaction, BTRAN[1:0], indicates whether the next bus
cycle will be address-only, sequential or non-sequential. It is
enabled by the grant signal and is ahead of the bus cycle to
which it refers.
• The address bus, BA[31:OJ.
• Bus transfer direction, BWRITE.
• Bus protection signals, BPROT[1:0], which indicate instruction
or data fetches and supervisor or user access.
• The transfer size, BSIZE[1:0], specifies a byte, half-word or
word transfer.
• Bus lock, BLOK, allows a master to retain the bus to complete
an atomic read / modify-write transaction.
• The data bus, BD[31:0], used to transmit write data and to
receive read data. In an implementation with multiplexed
address and data, the address is also transmitted down this
bus.
A slave unit may process the requested transaction
immediately, accepting write data or issuing read data
on ED[31:0], or signal one of the following responses:
• Bus wait, BWAIT, allows a slave module to insert wait
states when it cannot complete the transaction in the
current cycle.
• Bus last, BLAST, allows a slave to terminate a
sequential burst to force the bus master to issue a new
bus transaction request to continue.
• Bus error, BERROR, indicates a transaction that cannot
be completed. If the master is a processor it should
abort the transfer.
Bus Reset:
The ASB supports a number of independent on-chip
modules, many of which may be able to drive the data
bus (and some control lines). Provided all the modules
obey the bus protocols, there will only be one module
driving any bus line at any time.
If two or more modules power-up trying to drive bus
lines in opposite directions, the output drive clashes
may cause power supply crow-bar problems which may
prevent the chip from powering up properly at all.
Correct ASB power-up is ensured by imposing an
asynchronous reset mode that forces all drivers off the
bus independently of the clock.
 Advanced Peripheral Bus – APB

It is a simple, static bus which operates as a stub on an

ASB to offer a minimalist interface to very simple
peripheral macrocells.
The bus includes address PADDR[n:0] and read and
write data PRDATA[m:0] and PWDATA[m:0], where m is
7, 15 or 31), a read/write direction indicator (PWRITE),
individual peripheral select strobes (PSELx) and a
peripheral timing strobe (PENABLE). APB transfers are
timed to PCLK, and all APB devices are reset with
PRESETn.
 Advanced High Performance Bus - AHB
The AHB is intended to replace the ASB in very high
performance systems. The following features
differentiate the AHB from the ASB:
• It supports split transactions, where a slave with a
long response latency can free up the bus for other
transfers while it prepares its data for transmission.
• It uses a single clock edge to control all of its
operations.
• It uses a centrally multiplexed bus scheme rather
than a bidirectional bus with tristate drivers.
• It supports wider data bus configurations of 64 or 128
bits.
Ref: ARM System-on-Chip Architecture
by Steve Furber 2nd Edition

Thank You