STM32 LOW POWER

MODES
EXAMPLE
LOW POWER
MODES
A/MHz Total power = Iaverage * V
% Iaverage = (IRun *TimeRun + IStandby * TimeStandby +
Run % Low power
Mode mode ISleep * TimeSleep + IStop *
TimeStop) / Timetotal

Run Run

Low power Low power

time

A/MHz

Average power consumption

time
 POWER-SAVING METHODS AND FEATURES
FOR STM32F4

Four oscillators on board Two PLLs

LSE: 32.768 KHz osc Main PLL (PLL) clocked by HSI or
LSI: 32kHz internal RC used for (independent HSE used to generate the System clock
watch dog) IWDG, optionally RTC and Auto (up to 168MHz), and 48 MHz clock for
Wake-Up (AWU) USB OTG FS, SDIO and RNG.
HSE (High Speed External Osc) 4 to 26 MHz
PLLI2S PLL (PLLI2S) used to generate
HSI (High Speed Internal RC): 16MHz +/-1
a clock to achieve HQ audio
precise time base with very low power performance on the I2S interface.
consumption (max 1μA).
optionally drives the RTC for AWU from
STOP/STANDBY mode.
 MORE POWER SAVING METHODS

Voltage regulator bypass

ART configuration

I/O configuration

Using direct memory access (DMA)

Code Optimization
 Entering low-power
STM32F4XX
modes:
LOW POWER • Executing the WFI (Wait For
MODES Interrupt) or WFE (Wait for
FEATURES - Event) instructions.
SLEEP • SLEEPONEXIT bit in the
Cortex-M4 with FPU SCR is
set on Return from ISR.
 STM32F4XX SYSTEM CONTROL REGISTER
31 5 4 3 2 1 0
Reserved SEVON Res. SLEEP SLEEP Res.
PEND DEEP ON
EXIT

Bits Name Function

[4] SEVONPEND Send Event on Pending bit
0: Only enabled interrupts or events can wakeup the processor,
disabled interrupts are excluded
1: Enabled events and all interrupts, including disabled
interrupts, can wakeup the processor.
[2] SLEEPDEEP Controls whether the processor uses sleep or deep sleep as its
low power mode:
0: Sleep
1: Deep sleep
[1] SLEEPONEX Configures sleep-on-exit when returning from Handler mode to
IT Thread mode
0: Do not sleep when returning to Thread mode.
1: Enter sleep, or deep sleep, on return from an interrupt
service routine.
 STM32F405/7XX POWER CONTROL REGISTER (PWR_CR):

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ODSWE
UDEN[1:0] ODEN
Reserved N
rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VOS FPDS DBP PLS[2:0] PVDE CSBF CWUF PDDS LPDS
Res.
rw
Reserved Rw rw rw rw rw rw rc_w1 rc_w1 rw rw

Bits Name Function

[1] PDDS Power-down deep sleep This bit is set and cleared by software. It
works together with the LPDS bit.
0: Enter Stop mode when the CPU enters deep sleep. The regulator
status depends on the LPDS bit.
1: Enter Standby mode when the CPU enters deep sleep.
[0] LPDS Low-power deep sleep : This bit is set and cleared by software. It
works together with the PDDS bit.
0: Voltage regulator on during Stop mode
1: Voltage regulator in low-power mode during Stop mode
 Entering the Stop mode
• WFI/WFE
• when the SLEEPDEEP bit in the Cortex®M4
with FPU System Control register is set.
• In Stop mode, the following features can be
STM32F405/7XX selected by programming individual control
STOP MODE: bits:
• Independent watchdog
• Real-time clock (RTC):
• Internal RC oscillator (LSI RC):
• External 32.768 kHz oscillator (LSE OSC)
 STM32F405/7XX STOP MODE:

Stop operating modes

Stop mode LPDS FPDS bit Wake-up latency
bit
STOP MR(Main regulator)
0 0 HSI RC startup time
HSI RC startup time + Flash wakeup time
STOP MR-FPD 0 1 from Power Down mode
STOP LP 1 0 HSI RC startup time +regulator wakeup
time from LP mode

HSI RC startup time + Flash wakeup time

STOP LP-FPD from Power Down mode + regulator
1 1
wakeup time from LP mode
 STANDBY MODE
In Standby mode, the following features can be selected by
programming individual control bits:
Independent watchdog (IWDG):

Real-time clock (RTC):

Internal RC oscillator (LSI RC):

External 32.768 kHz oscillator (LSE OSC):

 WAKEUP TIME FROM LOW POWER MODES
Low power mode Wakeup time in
Conditions μs
Sleep mode 1 Typ

Stop mode regulator in Run mode 13 Typ

regulator in low power mode
Stop mode 17 Typ
regulator in low power mode and
Flash in Deep power down mode
Stop mode 110 Typ

Standby mode 375 Typ