Design of a Low-Power 10-Bit DAC in 130 nm

CMOS Technology
Mamun Bin Ibne Reaz Md. Torikul Islam Badal
Centre of Advanced Electronic and Communication Engineering Centre of Advanced Electronic and Communication Engineering
Faculty of Engineering and Built Environment Faculty of Engineering and Built Environment
Universiti Kebangsaan Malaysia Universiti Kebangsaan Malaysia
Bangi, Malaysia Bangi, Malaysia
mamun@ukm.edu.my torikul.uniten@gmail.com

Abstract—Developing an accurate and fast digital to analog matching performances [5-8]. Binary scaled current switches
converter (DAC) to deal with varieties of readout tasks in the are frequently used to minimize the area [9, 10]. Smaller
new era of wireless communication. This paper reports the switches caused lower capacitance and reduced feed via
model design and measurements of common function DAC charge injections, which allows to achieve smaller glitches
readout systems useful RF devices. Primary aim of the newly with improve dynamic performance of the DAC [11, 12].
proposed DAC is to achieve low power utilization. The
developed system consists of a 10-bit DAC depending on a
current routing design in the presence of an amplifier AB
output of high-swing class. The proposed DAC is designed in
130 nm which consume only less than 0.6 mW power.

Keywords—Class AB amplier, CMOS, Current steering,

DAC, Low power

I. INTRODUCTION
Generally, Digital to Analog Converter (DAC) is
integrated in RF front tom convert an digital signal to analog
signal. To achieve high performance in the RF devices, a
DAC with excellent resolution, low power consumption,
small chip area, and high-swing is needed. A research has
been done to design a DAC with 10-bit resolution in
accordance to these specifications and serve the purpose.
DACs based on current steering and resistor ladders or
strings architectures are the most popular architecture among
all architectures [1-3]. They are highly useful for the
implementation in standard CMOS processes and render an
excellent compromise between power usage, occupied area,
and swiftness.
Fig. 1 displays the block diagram of the proposed DAC
design, where a binary weighted 9-bit current source matrix
forms the core component. The current from the 9-bit current
sources matrix is mirrored and switch via MSB between
current source or sink at the input to the current to voltage
converter to achieved 10-bit resolution. A current mirroring
is used to realize the current sink [4]. A class AB rail-to-rail
output trans-impedance amplier is employed in the current
to voltage converter to obtain high output swing and large
current-drive capability. Output amplier’s reference
potential is externally set via default at half of the power
supply voltage. An active cascode stage composed of two-
stages of a trans-conductance amplifier followed by a current
buffer is used in both blocks. This ensured the generation of
constant source-drain voltages in the current source matrix
and mirror as well increased the output resistance.
A single cell in the matrix must be constituted with a unit
current source and its corresponding switches to achieve best
This research is financially supported by the Universiti Kebangsaan
Malaysia, Malaysia. Project code: DIP-2017-003.
Fig. 1. Block diagram of the proposed DAC design.
This paper is organized as follows: Section II highlights
the design of the proposed DAC. Experimental results and
discussions are presented in Section III. Section IV
concludes the paper.
II. METHODOLOGY
The proposed DAC is designed based on the current
steering architecture. One restriction is the simplicity of
implementation of a high-swing output buffer and the other
is the ability to investigate DAC performance by changing
the LSB size as a function of current Id. Generally, use of an
N-bit DAC resolution produces an error lower than 0.5 LSB
(Least Significant Byte or Least Significant Bit). Depending
on DAC design, maximum error of the MSB (Most
Significant Byte or Most Significant Bit) value (current or
resistance) yields [2]:
ΔIMSB / IMSB ≤ (100%) / 2N currents (1)
ΔRMSB / RMSB ≤ (100%) / 2N resistors (2)
The standard deviation of MSB must be three times
lower to fulfill the N-bit resolution at 99% level of
confidence (~3σ) of a Gaussian distribution. Following
Pelgrom’s model [3] the area required to obtain the desired
matching for resistor and current-based architectures is
calculated:

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Δ(R) = AR / √(W.L) (3)
δ(I) = [ 1 / √(W.L) ] / √A2β + (2AVth . 100% / Vod) (4)
where  = μ0.C0x is the current gain factor, Vod = Vgs - Vth
is transistor over-drive voltage
For a given current, the peak over-drive voltage is
acquired for the largest length-to-width ratio. A rough
estimate of the required area can be obtained from the
abovementioned expression. However, a realistic comparison
requires the consideration of other elements such as switches,
interconnections, dummies, etc.
A. Current Sources Matrix
Fig. 2 illustrates the current source matrix that mirrors the
currents from the reference source (Iref). Equation (2) is used
to compute the size of the unit current source to ensure an
INL of ±0.5 LSB (with condence of 3σ). The area of the
current sources is minimized through the selection of width
to length ratio (W/L) to obtain an over-drive voltage 650
mV. A very low LSB current 100 nA is considered to
satisfy the requirement of low power consumption.
Equations (2) and (3) clearly show that the current deviation
is inversely proportional to the over-drive voltage, which in
turn proportional to the square root of the drain current.
These limitations forced to set a very small W/L ratio. For
instance, in the 9-bit current sources matrix the W/L ratio is
fixed at 0.5 μm/40 μm. The low output current and W/L ratio
resulted very high output resistance of the current sources.
The simulated output resistance of the LSB current source is
found to be 6 G.
B. Design of AB Ampliers
Class AB amplifier is designed to integrated into DAC.
Certainly, majority of the ampliers (except the output one)
do not need high output swing and large current-drive
capability. This allowed to use a single-stage OTA in all
cases. Conversely, the output amplier needed high output
swing and large output current. This enforced to design it as
a two stage operational amplier with rail-to-rail class AB
output stage. A brief description of these developed systems
is provided below. A folded cascode amplier conguration
is used to create each OTA. NMOS (OTA1-OTA3) is used in
input differential pair. The power consumption per OTA is
15μw.
Class AB Operational Amplier: Fig. 3 depicts the
schematic illustration of the designed amplifier in the
presence of a cascoded Miller compensator with assured
stability. This compensation provided a better power supply
rejection ratio (PSRR) and required a compensation
capacitance of approximately 2 to 3 times lower than
standard Miller compensation technique [5]. The simulated
gain and unity gain bandwidth are determined to be 115 dB
and 2 MHz, respectively. The power consumption is found to
be below 60 μw with the output current capability exceeded
to 10 mA for both source and sink operation modes.
C. Current Mirror and High-Swing Output Circuit
Fig. 4 depicts the circuit diagram for the designed current
mirror sink and the class AB rail-to-rail output amplier. The
circuit topology covered here is one that appears in many
monolithic ICs. It is a Widlar mirror without an emitter
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degeneration resistor in the follower (output) transistor. The
equal drain-source voltages of transistors M1 and M2 ensured
the equality of currents in the current mirror. This is obtained
via additional active cascode amplier. The sizes of
transistors M1 and M2 are chosen to match their currents at
better than half of the LSB current. The design of M1 and M2
is sketched on a common-centroid matrix. These sizing
ensured a matching error below 0.5 LSB for the maximum
current value. However, it caused a large time constant with
low trans-conductance and high capacitance of the mirror
and enhanced the rise time of the output signal by a factor of
3.
Fig. 4. Circuit diagram for current mirror and high-swing output.
III. RESULTS AND DISCUSSION
Although the DAC output stage allowed the rail-to-rail
swing, the design parameters are chosen to set the output
voltage values within a slightly smaller range. Besides,
nonlinear measurements are performed for accurate
characterization of the static behavior. Reveals the measured
integral (INL) and differential (DNL) nonlinearity for a
typical DAC. The maximum of INL and DNL values are
found to be Ĭ0.4 LSB and Ĭ0.3 LSB, respectively. These
results on linearity, the output range and the LSB size are
found to be in very good agreement with the simulations
data. A normal distribution tted to the INL showed the
maximum (with 3ί condence level) value of 0.42 LSB.
Out of total 20 tested DACs only three are found to possess
short regions with INL value higher than 0.42 LSB. The
maximum value of visually estimated DNL excluding those
in the long negative tail is determined to be 0.42 LSB. Out of
20 tested DACs only four exhibited single states with
maximum DNL higher than 0.42 LSB.
A. DAC Performance versus Supply Voltage
Results for 3.3V and 2.9 V are observed to be almost
identical except a slight difference in the offset of the transfer
curve. This is expected because the externally applied
reference voltage Vref-out is scaled together with the supply
voltage. For supply voltages below 2.9 V the circuit
remained fully operational but the output current and LSB
voltage gradually decreased. This decrease in output and
reference currents is attributed to the deterioration of OTA1
– OTA3 operation as depicted earlier in Fig. 2. The limiting
case for superior operation happened for 1.9 V of the supply
voltage. This is slightly higher than half of the default supply
voltage. For supply voltage of 1.9 V, the simulation results
showed that the current sources remained in the saturation
region as expected. This is re-affirmed from the
measurement of good linearity (providing about 300 mV of
over-drive voltage). The operation of the circuit at such a low















 
voltage supply clearly demonstrated the robustness of the
proposed design.
B. Power Consumption
The power consumption of the DAC is examined for
those supply voltages that confirmed proper circuit operation
and the results are shown in for 1.9V supply voltage. Using
the default 3.3 V supply, the power consumption is
determined from 0.45 mW (Bdec low) up to 0.6 mW (Bdec
high) depending on input code value. A non-monotonic
relationship between DAC input code and power
consumption originating from the MSB switching between
the current matrix sources and the current mirror is
displayed. For smaller voltages, similar shapes are revealed
but with lower absolute power. As the supply voltage is
decreased to 2.9 V a linear decrease in the power
consumption is evidenced. This is because the DAC currents
are not affected due to this decrement. However, further
decrease of supply voltage below 2.9 V strongly affected the
DAC currents. Accordingly, the reduction in the power
consumption is much more pronounced. For 1.9 V supply,
the power consumption is discerned to be only Ĭ0.1 mW.
The minimum transistor dimension Ĭ 0.4/0.35 is chosen
for the LSB switch. Despite their small dimensions, the
resistance of the switches was negligible compared to the
resistance of the current sources, which were about six orders
of magnitude higher. These smaller switches caused lower
capacitance. The active cascode stages as shown in Fig. 2 are
used to make the drain current independent of the error
associated with the channel modulation factor. An equal
drain potential on both sides of the current mirrors is ensured
by setting their reference potential. Besides, the active
cascode circuit strongly enhanced the output resistance of
current source. Fig. 5 describes the output of the proposed
DAC and the layout of the DAC is shown in Fig. 6.
Results obtained from the proposed design are compared
with the existing state-of-the-art 10-bit DAC designs to
demonstrate the improvements. Table I enlists the relevant
parameters for all existing designs in addition to the
proposed one. The designs [7] and [8] are presented as a
general overview because the same current steering
architecture is used. Both designs are aimed mainly at higher
update rates in terms of power consumption by using a
current output. The design described in [9] also used a
current output, but the prime objective of this work was to
design a general purpose static DAC. In opposition, the
power consumption in [9] is found to be relatively higher
without quantitative estimate of the conversion rate.
Earlier, an interesting 10-bit resistor ladder DAC (static)
was presented [10] that possessed very low power
consumption of 70 μw (analog part) and provided voltage
output. Moreover, the lack of output buffer and the presence
of high output resistance (40 k) limited its driving
capabilities. Use of resistor string architecture is also
acknowledged [11], where the DAC revealed the closest
functionality to the presented design because it acquired a
voltage output having rail-to-rail class AB output amplier.
The proposed design consumes low power of 0.1 mW and
chip area of 0.18mm2 which are less compare to others
design in table 1.
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TABLE I. COMPARISON WITH OTHER DACS
Performance [7] [8] Present work
Architecture Current string Current string Current string
Resolution (bit) 10 10 10
Technology 350 nm 180 nm 130 nm
Area(mm2) 0.55 0.35 0.18
Power
7.8 22 0.1
dissipation (mw)
IV. CONCLUSION
A 10-bit CMOS DAC read out system having low-power,
small-area, and high-swing is designed in this research. The
circuit core area occupied 0.18 mm2. The DAC is
demonstrated to be fully functional and the experimental
results on performance evaluation are in good in agreement
with simulations data. Especially, power consumption is
determined to be as low as 0.6 mW. The present design can
be diversely employed for general purpose block in all RF
front end due to its low-power requirement, small-area chip
area.
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Fig. 2. Circuit design showing various current sources and active cascode stages.

Fig. 3. Schematic diagram of a class AB amplier.

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Fig. 5. The output waveform by changing the input code of one LSB at 100 kHz clock frequency.

Fig. 6. The layout of proposed class AB amplifier.

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