2020 IC Design Contest

Full-Custom Category
A 32K-Hz low power RC oscillator

I. General Descriptions:
With the vigorous development of the Internet of Thing(IoT) devices, the design of low
power consumption becomes more and more important. Because each device in the Internet of
Things requires precise time control circuits to ensure that the device starts or transmits data
synchronously at the correct time. On the other hand, under the requirements of small size, we
can not use too many external components, so there are low power consumption,
miniaturization design requirements. The theme of this competition is to design a 32 kHz clock
circuit to reduce power consumption as much as possible while maintaining a certain degree
of stability.
Fig. 1 shows the basic architecture of an RC oscillator. The scheme results in an oscillation
period of RC + tdelay, where tdelay is the delay of the comparator and resets logic. The main
advantage of this architecture is the low dependence between the oscillation frequency and
current. In this contest, finding the appropriate R and C values and designing the required
frequency is the first important task.

Fig. 1. A basic RC oscillator

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 For low power and high accuracy design, the tradeoffs and some considerations are shown
as bellow:
1. The current can be reduced with low voltage swing at V1 and V2, but the face of the
comparator offset which is temperature-dependent, a given offset affects the period.
2. The input-referred noise of comparator and current source noise leads to timing
inaccuracy.
3. The speed of the comparator is limited by the low current consumption itself.
4. At the low value of the current source, I, the temperature-dependent leakage current in
switches can affect on period.
Due to the statical model is not include in the CIC virtual process library, you may not see the
random noise and mismatch effects in the simulation stage. Although 1 and 2 are not easy
estimation in this contest, it is still important to you understand how its doses in a practical
circuit. Now you will focus on the 3 and 4 then design your circuit parameters in this contest.
Fig. 2 show a simple schematic and its waveforms. Note that the key nodes V1, V2 and PH in
your design should generate a similar waveform as shown in Fig. 2.

Fig. 2. A simple schematic of RC oscillator and its waveforms

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 Fig. 3 shows the complete circuit architecture circuit. the comparator is a key component
in the test. A PMOS input pair is chosen due to the low voltage swing at V1 and V2 in Fig. 2. A
constant –gm biasing leads to nominally constant bandwidth of comparator across temperature
if Rb is temperature independent. You need to design a proper biasing current which is almost
dominant the total power consumption and considers the sufficient bandwidth for target
oscillating frequency. In this contest, you are asked to design the size of the transistors as well
as the value of resistors and capacitors based on this architecture. Except for the ideal output
capacitor load, the additional circuits will not be allowed. Fig. 3 have provided all the circuit
architectures, the detailed circuit diagrams of the comparator and inverter are shown at the top of
Fig. 3. Please know that all of the components in Fig. 3 must be drawn in the layout.

Fig. 3. Complete schematic of RC oscillator

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II. Design Constraints:
1. Please use CIC 0.18um 1.8V 1P6M CMOS virtual process to design the whole circuit. The
device model is HSPICE Level 49. The final results should include the netlist, layout and all
the verification files (DRC and LVS reports).
2. Please use RNHR1000 poly resistor when implementing resistors, you can refer to “CIC
0.18um 1.8V/3.3V 1P6M Virtual Mixed Mode/RFCMOS Process Device Formation” page 11
for details.
3. This circuit operates only with a positive supply voltage. No negative bias source is allowed in
your design.
4. Besides the above requirements, the post-simulation (R+C+CC extraction, no inductance is
necessary) results of this circuit should also meet the following specifications under the typical
transistor parameters (TT corner):
 Oscillator frequency(PH)：32 KHz ± 5% in temperature sweep from 0℃ to 60℃
 Duty cycle: 50 % ± 5% in temperature sweep from 0℃ to 60℃

III. Scoring:
1. Acceptance criteria: Finish layout without any DRC/LVS error and the post-simulation
results of your design meet all specifications described in constraint 4 in section II.
2. Ranking method: Satisfying the acceptance criteria is the basic requirement. The ranking
is based on the maximum value of averaging current consumption(here is dedicated as
“ivdd_rms”) acquire from simulation results as shown in Fig. 4. In this plot, the X-axis is
the number of sweep times from 0℃ to 60℃ and the Y-axis shows the “dutycycle”,
“frequency” and “ivdd_rms”, respectively. You can use the testbench to examine your design
whether if it matches the requirements or not.

Fig. 4. Simulation results from tb_RCOSC.mt0

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3. Please be noted: If any of the acceptance criteria is not satisfied, the ranking will be affected
even if his/her power consumption is less than other teams who satisfy all the specifications
but with higher power consumption.
4. The principle of scoring is based on the complete design in the contest. However, even
though your design cannot be finished in time, TSRI allows the designers to upload their
results before the deadline of the contest. If the number of teams with “complete design” is
less than the number of awards, the incomplete designs might be granted.

IV. The following rules should be followed

EDA Tools:
1. Follow the instructions in the entry manual.

Others:
1. TSRI will provide the unified test bench to consist of the scoring criteria.
2. Netlist file naming: the subckt name of the netlist file should be “RCOSC.spi”, the top cell
should be named as “RCOSC”, and output node is “ph”. Supply power is “vdd” and ground is
“gnd”. Please be noted that the total circuit nodes are referred and followed the example:
.subckt RCOSC en ph phb vdd gnd * note: pin sequence is important
MM1 net1 net2 Vdd Vdd P_18 L=x W=y
…..
…..
.ends RCOSC
3. GDSII file is named as “RCOSC.gds” and the top cell name is “RCOSC”
4. It’s not necessary to do the antenna check when doing the DRC but other items should be clean
expect the metal density error
5. Please copy the testbench file in Section V.
6. Please tar the “RCOSC.spi” and “RCOSC.gds”, name this tar file as “grad_fullcustom.tar” and
put it to your home directory.

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V. Testbench File

** 2020 IC Contest

.LIB "cic018.l" tt
.INC "RCOSC.spi"

xRCOSC en ph phb vdd gnd RCOSC

c1 ph gnd 1p
c0 phb gnd 1p

vdd vdd gnd PWL 0 0 1e-6 0 1.1e-6 1.8

ven en gnd PWL 0 0 2e-6 0 2.1e-6 1.8
********************************************************************
*Analysis
********************************************************************
.OP
.OPTION POST
.TRAN 0.1u 1000u sweep temp 0 60 10
.PROBE v(ph) v(phb)
.MEAS TRAN TU TRIG v(ph) val=0.9 cross=15 targ v(ph) val=0.9 cross=16
.MEAS TRAN TD TRIG v(ph) val=0.9 cross=15 targ v(ph) val=0.9 cross=17
.MEAS DutyCycle PARAM='TU/TD'
.MEAS Frequency PARAM='1/TD'
.MEAS TRAN IVdd_rms rms i(vdd) from=600u to=1000u
.END

VI. Technology file and testbench download

Open termainl and type the following instructions：

Vitrual process 0.18um

/cad/icc2020/VP/cpall.csh

Testbench
cp /cad/icc2020/agf/tb_RCOSC.sp ~

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