Professional Documents
Culture Documents
1
OUTLINE
2.1 Introduction
What is an Instruction Set ?
2.2 Machine Instruction Characteristics
Elements of Machine Instruction
Operand Locations
Instruction Representation
Instruction Types
2.3 Instruction Set Design
Types of Operands
Types of Operations
Addressing Mode
Instruction Format
2.4 Instruction Cycle
2.5 Interrupts
2.6 Instruction Cycle Data Flow
2.7 Processor Structure and Function
Processor Organization
Register Organization
22
2.1 INTRODUCTION
Much of the computer architecture/organization
is hidden from a high level language programmer
Shouldn’t care what the underlying architecture really is
Machine Code
encoded in binary – for machines to work with
From Designer’s
It provides the Point of view
functional requirements for the CPU.
Implementing the CPU is a task that in large part involves
implementing the machine instruction set.
We will investigate
the design of the instruction set
The impact of the set on the design of the
overall computer system
57
ELEMENTS OF A MACHINE INSTRUCTION
Each instruction must contain all the information
required by the CPU for execution
7
OPERAND LOCATIONS
Where Can Operands Be?
Source and result operands can be in one of the three
areas:
Main memory
Memory address must be supplied
CPU register
8
INSTRUCTION REPRESENTATION
With in a computer, each instruction is
represented by sequence of bits
Each instruction has a unique bit pattern
10
INSTRUCTION REPRESENTATION…
Difficult for the programmers to deal
with binary representation of machine
instruction
Hence, it is common to use a symbolic
representation of machine instruction
Opcodes
Represented by abbreviations called mnemonics --- that
indicate the operation
Operands
Also represented symbolically
Example
ADD R, Y
13
11
INSTRUCTION REPRESENTATION…
13
12
Consider a high-level language instruction that could be
expressed in a language such as BASIC or FORTRAN.
For example, X=X+Y
This statement instructs the computer to add the value stored in
Y to the value stored in X and put the result in X. How might
this be accomplished with machine instructions?
Let us assume that the variables X and Y correspond to locations
513 and 514. If we assume a simple set of machine instructions,
this operation could be accomplished with three instructions:
1. Load a register with the contents of memory location 513.
2. Add the contents of memory location 514 to the register.
3. Store the contents of the register in memory location 513.
13
INSTRUCTION TYPES
An instruction set must be functionally complete
Sufficient enough to express any of the instructions
from a high level language
Characters
Logical Data
Bits or flags
17
TYPES OF OPERATIONS
Different machines support different opcodes:
Data Transfer
Arithmetic
Logical
Conversion
I/O
System Control
Transfer of Control
18
DATA TRANSFER
Most fundamental type of instructions
Must specify the following things
Location of source and destination operands
memory, register …
Length of data to be transferred
Full word, half word …
E.g.
Move, Store, Load, Push, Pop
In terms of CPU action
data transfer operations are the simplest type
19
ARITHMETIC
Performed by ALU
Basic arithmetic operations provided by
most
machines are:
Add, Subtract, Multiply, Divide
Signed Integer
Floating point
May include
Increment
Decrement
Negate
Absolute
20
LOGICAL
Operations that manipulate individual bits of a word
Bitwise operations
AND, OR, exclusive-OR (XOR)
NOT (one’s complement)
In addition a variety of shifting and rotating functions
Logical shift
Shifts bits of word either to the left or right
On one end the bit shifted out is lost
Arithmetic shift
Treats the data as a signed integer and does not shift the sign bit
Rotate/Cyclic shift
Preserves all of the bits being operated on
21
SHIFT AND ROTATE OPERATIONS
0
logical
shift
shift in 0
arithme
tic
shift
keep sign !
rotate
22
CONVERSION
Change the format of data or operate on
the format of data
Binary to Decimal
ASCII to EBCDIC
23
INPUT/OUTPUT
Transfer data
from the computer to peripheral devices
From peripheral devices to the computer system
24
SYSTEM CONTROL
Reserved for use by the operating system
Instructions executed while the processor is in
certain privileged mode
Privileged instructions
CPU needs to be in specific state
25
TRANSFER OF CONTROL
Alter the flow of program
i.e. change the sequence of instruction execution
Update the PC to a specific address
Most common such type of operations are:
Branch, Skip, Procedure call
26
TRANSFER OF CONTROL…
Branch
Also called jump instruction
Its operand is the address of the next instruction to be fetched
and executed
Two types of branches
Conditional and Unconditional
Conditional Branch
A branch is made if certain condition is met
E.g.
BRP X
Branch to instruction at location X if result is positive
BRZ X
Branch to instruction at location X if result is zero
BRE R1,R2,X
Branch to X if contents of R1 is equal to contents of
R2
Unconditional branch
E.g. 27
BR X
Branch to instruction at location X
TRANSFER OF CONTROL…
Branch Instructions
28
TRANSFER OF CONTROL …
Skip
Implies that the next instruction be skipped
Contains an implied address
Can be of two types:
Unconditional
Skip (i.e. unconditionally increment PC to skip the next
instruction)
Conditional
29
ADDRESSING MODES
The manner in which each address field
specify operand location
Notations:
A = Contents of an address field in the instruction
R = Contents of an address field in the instruction that refers to a
register
(X) = Contents of memory location X or register X
EA =Effective address of the location containing the referenced
operand
30
ADDRESSING MODES…
Types of addressing modes
Immediate
Direct
Indirect
Register
Register Indirect
Displacement
Stack
31
IMMEDIATE ADDRESSING
The instruction itself contains the operands value
Operand is part of instruction
Operand = A
E.g. ADD 5
Add 5 to contents of accumulator
5 is operand
Opcode Operand
33
DIRECT ADDRESSING
Address field contains address of operand
Effective address EA = A
Operand = (A)
E.g. ADD A
Add contents of memory location A to accumulator
One more memory access needed to fetch the operand
No additional calculations required to work out
effective address
Number of memory locations can be referenced,
that limited, due to limited width of
the field
Common
Limited addressgeneration
on earlier space of computers
34
DIRECT ADDRESSING DIAGRAM
Opcode A
Memory
Operand
35
INDIRECT ADDRESSING
A (the address field) refers to a memory location
which contains the address of operand
Multiple (two) memory accesses to find
operand
Fetch EA
Fetch operand
Access the memory twice, hence slower
EA = (A)
Operand = ((A))
E.g. ADD (A)
Look in A, find address (A) and look there for operand
Range of EA increased
36
Large address space
2n ,where n = word length
INDIRECT ADDRESSING DIAGRAM
Opcode A
Memory
Operand
37
REGISTER ADDRESSING
Similar to direct addressing
The address field refers to a register than a main memory address
EA = R
Operand = (R )
Very small address field needed
Shorter instructions
Faster instruction fetch
No memory access required
Very fast execution
Very limited address space
Small number of registers can be referenced
38
REGISTER ADDRESSING DIAGRAM
Opcode R
Registers
Operand
39
39
REGISTER INDIRECT ADDRESSING
Similar to indirect addressing mode
Operand is in memory pointed to by contents
of
register R
EA = (R)
Operand =((R ))
Registers
Operand
41
DISPLACEMENT ADDRESSING
Very powerful addressing mode
Combines
direct addressing and
Register indirect addressing
Instruction needs to have two address fields
At least one of which is explicit
EA = A + (R)
Address field hold two values
A = base value
R = register that holds displacement
or vice versa 41
42
DISPLACEMENT ADDRESSING DIAGRAM
Instruction
Opcode R A
Memory
Registers
+
Operand
43
RELATIVE ADDRESSING
A version of displacement addressing mode
Implicitly references the PC register
R = Program counter, PC
EA = A + (PC)
Saves bits
44
BASE-REGISTER ADDRESSING
Referenced register contains memory address
R holds pointer to base address
45
INDEXED ADDRESSING
Address field contains memory address
A = base
The referenced register contains a
displacement from that address
R = displacement
EA = A + ( R )
Good for arrays and performing accessing
iterative operations
Auto indexing
increment and decrement
46
INDEXED ADDRESSING…
Combinations
Indirect addressing with
indexing
Post indexing
The indexing performed after the indirection
EA = (A) + (R)
Good to access a block of data of a fixed format
Pre indexing
The indexing performed before the indirection
EA = (A+(R))
Used to construct a multiway branch table 47
STACK ADDRESSING
A stack
The stack mode of addressing is a form of implied
addressing
The machine instructions need not include a memory
reference but implicitly operate on the top of the
stack
48
numerical example
Address Memory
Addressing Mode Effective Address Content of AC
PC = 200 200 Load to AC Mode
Immediate Address Mode 201 500
201 Address = 500
Direct Address Mode 500 800
Indirect Address Mode 800 300 R1 = 400 202 Next instruction
Register Mode 400
Register Indirect Mode 400 700 XR = 100
Relative Address Mode 702 325
399 450
Indexed Address Mode 600 900
Autoincrement Mode 400 700 AC 400 700
R1 = 400
600 900
500 + 202 (PC)
R1 = 400 (after) 702 325
500 + 100 (XR)
R1 = 400 -1 (prior)
800 300
CPU design plan
RISC- reduced instruction set computer
This is small or reduced set of instructions.
51
INSTRUCTION FORMAT
It defines the layout of the bits of an instruction, in
terms of its constituent parts
More than one format used in a given instruction set
with respect to the operand fields in the instructions.
52
Instruction Formats
Three-Address Instructions
● ADD R1, R2, R3 R1 ← R2 + R3
Two-Address Instructions
● ADD R1, R2 R1 ← R1 + R2
One-Address Instructions
● ADD M AC ← AC + M[AR]
Zero-Address Instructions
● ADD TOS ← TOS + (TOS – 1)
RISC Instructions
● Lots of registers. Memory is restricted to Load & Store
54
Instruction Formats
55
Instruction Formats
60
FETCH CYCLE
Program Counter (PC) holds address of next
instruction to be fetched
Processor fetches instruction from memory
location pointed by PC
Increment PC
61
EXECUTE CYCLE
Processor interprets instruction and performs required
actions
Processor-memory
data transfer between CPU and main
memory
Processor -I/O
Data transfer between CPU and I/O
module
Data processing
Some arithmetic or logical operation on
data
Control
Alteration of sequence of execution
e.g. jump
Execution of an instruction may involve a combination of 19
62
above actions
EXAMPLE OF PROGRAM
EXECUTION
20
63
2.5 INSTRUCTION CYCLE DATA FLOW
65
DATA FLOW (FETCH DIAGRAM)
66
DATA FLOW (EXECUTE)
May take many forms
Depends on instruction being executed
May include
Memory read/write
Input/Output
Register transfers
ALU operations
67
Instruction pipeline
organizational approach, which improve the processer
performance
various stages can be worked on simultaneously
68
• Fetch instruction (FI): Read the next expected instruction into a
buffer.
• Decode instruction (DI): Determine the opcode and the operand
specifiers.
• Calculate operands (CO): Calculate the effective address of each
source operand. This may involve displacement, register indirect,
indirect, or other forms of address calculation.
• Fetch operands (FO): Fetch each operand from memory.
Operands in registers need not be fetched.
• Execute instruction (EI): Perform the indicated operation and
store the result, if any, in the specified destination operand
location.
• Write operand (WO): Store the result in memory
69
Instruction pipeline
70
2.6 INTERRUPTS
Mechanism by which other modules (e.g. I/O)
may
interrupt normal processing of the processor
Interruption of the normal sequence of execution
Provided to improve processing efficiency
Common classes of interrupts
Program
e.g. overflow, division by zero
Timer
Generated by internal processor timer
Used in pre-emptive multi-tasking
I/O
from I/O controller
Hardware failure
e.g. power failure, memory parity error 21
71
Instructioncycle so far consists of the
following sub cycles:
Fetch
Execute
Interrupt
72
INTERRUPT CYCLE
Added to instruction cycle
Processor checks for interrupt
Indicated by an interrupt signal
If no interrupt, fetch next instruction
If interrupt pending:
Suspend execution of current program
Save context
Set PC to starting address of interrupt handler
routine
Process interrupt
Restore context and continue interrupted 22
73
program
INSTRUCTION CYCLE WITH INTERRUPTS
74
TRANSFER OF CONTROL VIA INTERRUPTS
75
MULTIPLE INTERRUPTS
Two approaches to deal with multiple interrupts
Disable interrupts
Processor will ignore further interrupts
whilst processing one interrupt
Interrupts remain pending and are checked after first
interrupt has been processed
Interrupts handled in sequence as they occur
Define priorities
Low priority interrupts can be interrupted by higher
priority interrupts
When higher priority interrupt has been
processed, processor returns to previous interrupt 25
MULTIPLE INTERRUPTS – SEQUENTIAL
DISABLE INTERRUPTS
77
MULTIPLE INTERRUPTS – NESTED
PRIORITIZED INTERRUPTS
78
TIME SEQUENCE OF MULTIPLE INTERRUPTS
79
DATA FLOW (INTERRUPT)
Simple and Predictable
Current PC saved to resumption after
allow interrupt
Contents of PC copied to MBR
Special memory location (e.g. stack
pointer) loaded to MAR
MBR written to memory
PC loaded with address of interrupt
handling routine
Next instruction (first of interrupt handler)
can
be fetched 80
DATA FLOW (INTERRUPT DIAGRAM)
81
2.7 Processor structure and Function
Processor Organization
To understand the organization of the CPU,
recall the requirements placed on the CPU:
Fetch instruction
Interpret instruction
Fetch data
Process data
Write data
83
83
PROCESSOR ORGANIZATION…
Detailed view of a CPU
Indicates
Data transfer and logic control paths
Internal processor bus
84
84
REGISTER ORGANIZATION
Registers
CPU must have some working space
Temporary storage
Top level of memory hierarchy
Number and function vary between processor
designs
One of the major design decisions
85
85
REGISTER ORGANIZATION…
Registers classified into two groups:
User visible registers:
Can be referenced by assembly language
instructions
86
86
USER VISIBLE REGISTERS
Can be categorized as follows:
General purpose registers
Data registers
Address registers
Condition codes
87
87
USER VISIBLE REGISTERS…
General Purpose Registers
Can be assigned variety of function by the
programmer
May be true general purpose
May be restricted
May be used for data or addressing
Data Registers
Used only to hold data
Accumulator
88
88
USER VISIBLE REGISTERS…
Address registers
Hold addresses
Can be
General purpose or
Devoted to particular addressing mode
89
89
USER VISIBLE REGISTERS…
CONDITION CODES
Sets of individual bits , also called flags
Each bit set by CPUhardware as the result
of operations:
E.g. Arithmetic operation results could be
Positive, negative, zero, overflow
Can be read (implicitly) by programs
e.g. Jump if zero
Can not (usually) be set by programs
90
90
CONTROL & STATUS REGISTERS
Refers to different registers employed to
control the operation of the CPU
Most not visible to the user
Register essential during instruction cycle are
Program Counter (PC)
Instruction Register (IR)
Memory Address Register (MAR)
Memory Buffer Register (MBR)
91
91
CONTROL & STATUS REGISTERS…
Program Status Word (PSW)
A register that contain status information
Usually contains
Condition codes
Status information
Common fields or flags include
Sign, zero, carry, equal, overflow, supervisor,
interrupt enable/disable
Note that CPU design and Operating
system design are closely linked
92
92
2.8 INTERCONNECTION STRUCTURES
A computer consists of a set of components
All the units must be connected
The collection of paths connecting various units
Interconnection structure
Different type of connection for different type of
unit
Memory
Input / Output
CPU
There are a number of possible interconnection
structures, the most common are: 29
93
Single and multiple BUS structures
MEMORY CONNECTION
Receives and sends data
Receives addresses (of locations)
94
INPUT/OUTPUT CONNECTION
Similar to memory from computer’s viewpoint
Output
Receive data from computer
Send data to peripheral
Input
Receive data from peripheral
Send data to computer
95
CPU CONNECTION
Reads instruction and data
Writes out data (after processing)
96
BUS INTERCONNECTION
What is a BUS ?
A communication pathway connecting two or more
devices
Consists of multiple lines, each line capable of transmitting
signals representing binary 1 or binary 0
97
34
DATA BUS
Carries data
Remember that there is no difference
between “data” and “instruction” at this
level
Widthis a key determinant of
performance
8, 16, 32, 64 bit
98
ADDRESS BUS
Identify the source or destination of data
e.g. CPU needs to read an instruction (data) from a
given location in memory
Buswidth determines maximum memory
capacity of system
e.g. 8080 has 16 bit address bus giving 64k address
space
99
CONTROL BUS
10
0
Operation of bus
If one module wishes to send data to another,
it must
Obtain the use of the bus
Transfer data via the bus
10
1
BUS INTERCONNECTION...
Single Bus Problems
If many number of devices are connected to a
single bus, performance will suffer:
Reason
More devices, the greater the bus length, the
greater the propagation delay
Co-ordination of bus use can adversely affect
performance
The bus becomes a bottleneck as the aggregate
data transfer approaches the capacity of bus
Solutions
• Increasing the data rate that the bus can carry
• Using the wider bus
Most 39
10
systems use multiple buses to overcome 2
these problems
BUS INTERCONNECTION...
Multiple Buses
A Traditional Bus
Architecture
10
3
BUS INTERCONNECTION...
Multiple Buses…
A High-speed Bus
Architecture
10
4
Evaluate A*B using
a. 3-address format
b. 2-address format
2. Take 10011010
c. Logical right shift(2-bit)
d. Arthimetic left shift(2-bit)
e. Rotate left (2 bit)
10
5
END of Chapter Two
71
10
6