COE 485 Sem 1, 2023

Advanced Computer Architecture

Pipeline Control
 Control Signals
PCSrc
M
u

EX/MEM
x
IF/ID

ID/EX

MEM/WB
Add
Shift Branch
left 2

RegWrite
4
ALUSrc
Zero MemtoReg
Add
MemWrite

Regs M ALU M
u u
Instr. x Data x
PC Mem Mem

Sign ALU
extend Control MemRead

rt[20-16]
M ALUOp
u
rd[15-11] x

RegDst
 ALU Control Input
Instruction ALUOp Function code ALU Action ALU Control
Lw 00 xxxxxx Add 010
Sw 00 xxxxxx Add 010
Beq 01 xxxxxx Subtract 110
Add 10 100000 Add 010
Sub 10 100010 Subtract 110
And 10 100100 And 000
Or 10 100101 Or 001
Slt 10 101010 Set on less than 111
 Control Lines
Execution stage control Memory access WriteBack
lines control lines control lines
Instruction Reg ALU ALU ALU Branch Mem Mem Reg Mem2
Dst Op1 Op2 Src Read Write Write Reg

R-format 1 1 0 0 0 0 0 1 0

Lw 0 0 0 1 0 1 0 1 1

Sw x 0 0 1 0 0 1 0 x

Beq x 0 1 0 1 0 0 0 x
 Control Implementation
• Pipelining leaves the meaning of the 9
control lines unchanged
• Set control lines (to defined values) in each
stage for each instruction
• Extend pipeline registers to include control
information
• Nothing to control during IF and ID
• Create control information during ID
Generation/Propagation of Control

WB

Instruction Control
M WB

EX M WB

IF/ID ID/EX EX/MEM MEM/WB

 PCSrc W
B
Control M W
B
W
M E M
B
u

EX/MEM
x
IF/ID

ID/EX

MEM/WB
Add
Shift Branch
left 2

RegWrite

ALUSrc

MemtoReg
4

MemWrite
Zero
Add

Regs M ALU M
u u
Instr. x Data x
PC Mem Mem

Sign ALU
extend Control
MemRead
rt[20-16] ALUOp
M
u
rd[15-11] x
RegDst
 Example
lw $10, 20($1)
sub $11, $2, $3
and $12, $4, $5
or $13, $6, $7
add $14, $8, $9
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
Cycle 6
 Limitation: Pipeline Hazards (The
Laundary Example)
6 PM 7 8 9 10 11 12 1 2 AM

30 30 30 30 30 30 30 Time
T
Bag A: Control
a A bubble
puts 90m bubble
s
B in pipeline be-
k
tween dryer and
C
folder (done 9pm)
O
D
r Bag D: Cannot
d E complete until
e 10:30pm (one
r F folder available)
• Jim’s green socks : one in A other in D
• D depends on A  stall since folder busy
 Limits to Pipelining
• Hazards prevent next instruction from
executing during its designated clock cycle
– Structural hazards
• HW cannot support this combination of instructions
• Ex: Single person to fold and put clothes away
– Control hazards
• Branches stall the pipeline until the hazard
“bubbles” in the pipeline
– Data hazards
• Instruction depends on result of prior instruction
• Ex: Missing sock
 Conclusions (1/2)
• Optimal Pipeline
– Each stage is executing part of an instruction each
cycle.
– One instruction finishes during each clock cycle.
– On average, execute far more quickly

• What makes this work?

– Similarities between instructions
– Each stage takes about the same amount of time as
all others
 Conclusions (2/2)
• Pipelining a Big Idea: widely used concept

• What makes it less than perfect?

– Structural hazards: Need more HW resources
– Control hazards: Delayed branch
– Data hazards: an instruction depends on a previous
one