Sequential Circuits
Combinational Logic
• Combinational Logic:
– Output depends only on current input
– Has no memory
Oct 19, 2024 Sequential Circuits
Sequential Logic
• Sequential Logic:
– Output depends not only on current input but also
on past input values, e.g., design a counter
– Need some type of memory to remember the past
input values
Oct 19, 2024 Sequential Circuits
Oct 19, 2024 Sequential Circuits PJF - 4
Sequential Circuits
Circuits that we Information Storing
have learned Circuits
so far
Timed “States”
Oct 19, 2024 Sequential Circuits
Sequential Logic: Concept
• Sequential Logic circuits remember past inputs
and past circuit state.
• Outputs from the system are
“fed back” as new inputs
– With gate delay and wire delay
• The storage elements are circuits that are
capable of storing binary information:
memory.
Oct 19, 2024 Sequential Circuits
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Synchronous vs. Asynchronous
There are two types of sequential circuits:
• Synchronous sequential circuit: circuit output
changes only at some discrete instants of time. This
type of circuits achieves synchronization by using a
timing signal called the clock.
• Asynchronous sequential circuit: circuit output can
change at any time (clockless).
Oct 19, 2024 Sequential Circuits
Memory Devices
Latches A latch is a memory element whose
excitation signals control the state of the
device. A latch has two stages set and reset.
Set stage sets the output to 1. Reset stage
set the output to 0.
Flip-flops A flip-flop is a memory device that
has clock signals control the state of the
device.
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Terminology
• Flip-Flop – is a storage element that can have
its output state changed only on the edge of
the controlling clock signal.
• Positive-edge triggered – if the state changes
when the clock signal goes from 0 to 1.
• Negative-edge triggered – if the state changes
when the clock signal goes from 1 to 0.
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Terminology
The word latch is mainly used for storage
elements, while clocked devices are described as
flip-flops.
A latch is level-sensitive, whereas a flip-flop is
edge-sensitive. That is, when a latch is enabled it
becomes transparent, while a flip flop's output
only changes on a single type (positive going or
negative going) of clock edge.
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Latch Flip-flop
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Control of an alarm system
Set
Sensor
Memory On ¤ Off
Alarm
element
Reset
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Synchronous Sequential Circuits:
Flip flops as state memory
The flip-flops receive their inputs from the
combinational circuit and also from a clock
signal with pulses that occur at fixed
intervals of time, as shown in the timing
diagram.
Oct 19, 2024 Sequential Circuits
A simple memory element
A B
A simple memory element with NOT Gates
x x x
Building a NOT Gate with NAND
x x x x
x x f
x x 0 0 1
0 1 1 impossible
0 1 combinations
1 0 1
1 0 1 1 0
Thus, the two truth tables are equal!
A simple memory element with NAND Gates
x x x
Building a NOT Gate with NOR
x x x x
x x f
x x 0 0 1
0 1 0 impossible
0 1 combinations
1 0 0
1 0 1 1 0
Thus, the two truth tables are equal!
A simple memory element with NOR Gates
x x x
Basic Latch
A simple memory element with NOR Gates
A simple memory element with NOR Gates
A simple memory element with NOR Gates
Set Reset
A memory element with NOR gates
Reset
Set Q
Two Different Ways to Draw the Same Circuit
Circuit and Truth Table
R S R Qa Qb
Qa
0 0 0/1 1/0 (no change)
0 1 0 1
1 0 1 0
Qb 1 1 0 0
S
(a) Circuit (b) Truth table
NOR Gate NOR Gate Truth table
x1 x2 f
0 0 1
0 1 0
1 0 0
1 1 0
The SR Latch (NOR Version)
• The SR (Set-Reset) Latch
• And its operation
Oct 19, 2024 Sequential Circuits PJF - 28
Timing Diagram for the Basic Latch with NOR Gates
R S R Qa Qb
Qa
0 0 0/1 1/0 (no change)
0 1 0 1
1 0 1 0
Qb 1 1 0 0
S
(a) Circuit (b) Truth table
t1 t2 t3 t4 t5 t6 t7 t8 t9 t10
1
R
0
1
S
0
1
Qa ?
0
1
Qb ?
0
Time
(c) Timing diagram
The truth table for SR Flip Flop is as
shown below-
The above truth table may be reduced as-
INPUTS OUTPUTS
INPUTS OUTPUTS REMARKS
Qn Qn+1
S R (Next
(Present
State)
State) Qn Qn+1
S R (Next State) States and Conditions
(Present State)
0 0 0 0
0 0 1 1 0 0 X Qn Hold State condition S = R = 0
0 1 0 0
0 1 X 0 Reset state condition S = 0 , R = 1
0 1 1 0
1 0 X 1 Set state condition S = 1 , R = 0
1 0 0 1
1 1 X Indeterminate Indeterminate state condition S = R = 1
1 0 1 1
1 1 0 Indeterminate
Truth Table
1 1 1 Indeterminate
Characteristic Equation-
Draw a k map using the above truth table-
From here-
Qn+1 = ( SR + SR’ ) ( Qn + Q’n ) + Qn ( S’R’ + SR’ )
Qn+1 = S + QnR’
SR Latch (NAND version)
0 S’ S’ R’ Q Q’
Q 1
0 0
0 1 1 0 Set
1 0
Q’ 0
1 R’ 1 1
X Y NAND
0 0 1
0 1 1
1 0 1
1 1 0
Oct 19, 2024 Sequential Circuits PJF - 32
SR Latch (NAND version)
1 S’ S’ R’ Q Q’
Q 1
0 0
0 1 1 0 Set
1 0
Q’ 0
1 R’ 1 1 1 0 Hold
X Y NAND
0 0 1
0 1 1
1 0 1
1 1 0
Oct 19, 2024 Sequential Circuits PJF - 33
SR Latch (NAND version)
1 S’ S’ R’ Q Q’
Q 0
0 0
0 1 1 0 Set
1 0 0 1 Reset
Q’ 1
0 R’ 1 1 1 0 Hold
X Y NAND
0 0 1
0 1 1
1 0 1
1 1 0
Oct 19, 2024 Sequential Circuits PJF - 34
SR Latch (NAND version)
1 S’ S’ R’ Q Q’
Q 0
0 0
0 1 1 0 Set
1 0 0 1 Reset
Q’ 1
1 R’ 1 1 1 0 Hold
0 1 Hold
X Y NAND
0 0 1
0 1 1
1 0 1
1 1 0
Oct 19, 2024 Sequential Circuits PJF - 35
SR Latch (NAND version)
0 S’ S’ R’ Q Q’
Q 1
0 0 1 1 Disallowed
0 1 1 0 Set
1 0 0 1 Reset
Q’ 1
0 R’ 1 1 1 0 Hold
0 1 Hold
X Y NAND
0 0 1
0 1 1
1 0 1
1 1 0
Oct 19, 2024 Sequential Circuits PJF - 36
In this task we have to build an Active High D latch. D in
the name stands for DATA. The purpose of a D-Latch is to
avoid the invalid state. It avoids an in valid state because
it has only one input, which goes through the inverter. If
D is on 1, R becomes 0 and S becomes 1 and the output
we get is Q+ = 1 and Q’+ = 0. If D is on 0, R becomes 1
and S becomes 0 and the output we get is Q+ = 0 and
Q’+ = 1.
This circuit is called a DATA latch because it holds the
value.
The figure of the D Latch is shown below:
D Q+ Q+’
0 0 1
1 1 0
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An Even Simpler Example
with Feedback
Oct 19, 2024 Sequential Circuits PJF - 38
Let’s try to analyze this circuit
x f
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Terminology
• Basic Latch – is a feedback connection of two NOR
gates or two NAND gates, which can store one bit of
information. It can be set using the S input and reset
to 0 using the R input.
• Gated Latch – is a basic latch that includes input
gating and a control input signal. The latch retains its
existing state when the control input is equal to 0. Its
state may be changed when the control signal is
equal to 1.
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Terminology
• Two types of gated latches
(the control input is the clock):
• Gated SR Latch – uses the S and R inputs to
set the latch to 1 or reset it to 0.
• Gated D Latch – uses the D input to force the
latch into a state that has the same logic value
as the D input.
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Gated SR Latch
Oct 19, 2024 Sequential Circuits PJF - 42
Motivation
• The basic latch changes its state when the input
signals change
• It is hard to control when these input signals will
change and thus it is hard to know when the latch
may change its state.
• We want to have something like an Enable input
• In this case it is called the “Clock” input because it is
desirable for the state changes to be synchronized
Circuit Diagram for the Gated SR Latch
Circuit Diagram for the Gated SR Latch
This is the “gate”
of the gated latch
Circuit Diagram for the Gated SR Latch
Notice that these
are complements
of each other
Circuit Diagram and Characteristic Table
for the Gated SR Latch
Circuit Diagram and Graphical Symbol
for the Gated SR Latch
Gated SR latch with NAND gates
S
Q
Clk
Q
R
Gated SR latch with NAND gates
S
Q
Clk
Q
R
In this case the “gate” is
constructed using NAND
gates! Not AND gates.
SR Latch with Clock signal
Latch is sensitive to input changes ONLY when C=1
Oct 19, 2024 Sequential Circuits PJF - 51
D Latch
• One way to eliminate the undesirable indeterminate
state in the RS flip flop is to ensure that inputs S and
R are never 1 simultaneously. This is done in the D
latch:
Oct 19, 2024 Sequential Circuits PJF - 52
