Design Rules and Layout
• MOS layers and colour coding representation
• Design rules & layout
• Stick Diagrams
Design Rules
• Design rules are a set of geometrical
specifications that dictate the design of the
layout masks
• A design rule set provides numerical values
– For minimum dimensions
– For minimum line spacings
• Design rules must be followed to insure
functional structures on the fabricated chip
• Design rules change with technological advances
•The physical mask layout of any circuit to be manufactured using a particular
process must conform to a set of geometric constraints or rules, which are
generally called layout design rules.
•These rules usually specify the minimum allowable line widths for physical
objects on-chip such as metal and polysilicon interconnects or diffusion areas,
minimum feature dimensions, and minimum allowable separations between
two such features.
• If a metal line width is made too small, for example, it is possible for the line
to break during the fabrication process or afterwards, resulting in an open
circuit.
•If two lines are placed too close to each other in the layout, they may form an
unwanted short circuit by merging during or after the fabrication process.
•The main objective of design rules is to achieve a high overall yield and
reliability while using the smallest possible silicon area, for any circuit to be
manufactured with a particular process.
Why we need design rules?
• Design rules are supposed to prevent unworkable,
unreliable, or hard to implement constructs
• Design rules are introduced to preserve the
integrity of topological features on chip: to prevent
separate, isolated features from accidentally short
circuiting, or thin features from opening, or
Contacts from slipping outside the are a to be
contacted
• Each piece of fabrication equipment used in the IC
manufacturing process has limited accuracy.
• We need rules to ensure that the inaccuracy in the
fabrication will not result in malfunction IC.
3D Perspective
Polysilicon Aluminum
Design Rules Classification
• Minimum width
• Minimum spacing
• Surround
• Extension
Layout Diagram
Layout can be very time consuming
• Design gates to fit together nicely
• Build a library of standard cells
Standard cell design methodology
• VDD and GND should abut (standard height)
• Adjacent gates should satisfy design rules
• nMOS at bottom and pMOS at top
• All gates include well and substrate contacts
Types of Design Rules
• Micron Rules
• Lambda Rules
1. Micron Rules
Non-scalable or Micron Rules
Absolute Design Rules
Micron rules, in which the layout constraints such
as minimum feature sizes and minimum allowable
feature separations, are stated in terms of absolute
dimensions in micrometers
Based on absolute distances (e.g. 0.75μm)
Tuned to a specific process (details usually
proprietary)
Complex, especially for deep submicron
Layouts not portable
1. Micron Rules
• All min sizes and spacing specified by microns
• Standard in industry.
• Don’t have the multiples of λ.
2. Lambda Rules
Scalable Design Rules
Lambda rules, which specify the layout constraints in
terms of a single parameter (λ) and, thus, allow linear,
proportional scaling of all geometrical constraints
Based on scalable “coarse grid” -λ(lambda)
The unit of lambda is micrometer
Idea: reduce λ value for each new process, but
keep rules the same
Key advantage: portable layout
Key disadvantage: not everything scales the same
2)Lambda-based Design Rules
• Design based on parameter λ.
• Simple designing procedure.
• Min feature size is 2 λ.
• If design is accepted, mask produced on the
working ckt.
LAMBDA Based Design Rule
(λ Rule)
• Minimum width and minimum spacing
requirements between objects on the
different layers.
λ Rule for metal
Metal 1 Metal 2
Minimum width = 3λ Minimum width = 4λ
Separation = 3λ Separation = 4λ
λ Rule for metal
λ Rule for n+ diffusion, p+ diffusion and Polysilicon
n+ diffusion & p+ diffusion Polysilicon
Minimum width = 2λ , Separation = 3λ Minimum width = 2λ,Separation = 2λ
Separation between n+ (or) p+ diffusion and Polysilicon = λ
λ Rule for n+ diffusion, p+ diffusion and
Polysilicon
Contact Rules
• Contact size is 2x2
• Spacing to contact is 2
• Spacing to gate 2
Contact Cut
Metal 1 to Polysilicon
• Minimum width = 2λ , Separation = 4λ
Contact cut
Contact Cut
Metal 1 to n+ diffusion and p+ diffusion
• Separation = 2λ
Contact Cut
Metal 1 to n+ diffusion and p+ diffusion
Transistor Rules
• P-diffusion and n-diffusion should be 3λ
• Spacing between active should be 3λ
• Source and drain surrounded by 6λ
• Substrate-well contact 3λ
• Width of polysilicon 2λ
• Spacing to poly over field oxide is 2λ
λ Based Design Rule for
Transistors
CMOS Inverter Layout Diagram
CMOS Inverter Circuit Diagram
CMOS Inverter Layout Diagram
CMOS NAND Layout Diagram
CMOS NAND Circuit Diagram
CMOS NAND Layout Diagram
CMOS NOR Layout Diagram
CMOS NOR Circuit Diagram
CMOS NOR Layout Diagram
CMOS NOR Layout Diagram
Stick Diagrams
Stick Diagrams
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Stick Diagrams
VDD
VDD
X
X
x x x
x Stick
Diagra X
m
Gnd Gnd
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Stick Diagrams
VDD
VDD
X
X
x x x
x X
Gnd Gnd
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Stick Diagrams
• VLSI design aims to translate circuit concepts onto
silicon.
• stick diagrams are a means of capturing topography
and layer information using simple diagrams.
• Stick diagrams convey layer information through
colour codes (or monochrome encoding).
• Acts as an interface between symbolic circuit and the
actual layout. 47
Stick Diagrams
Does show all components/vias.
It shows relative placement of components.
Goes one step closer to the layout
Helps plan the layout and routing
A stick diagram is a cartoon of a layout.
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Stick Diagrams
Does not show
• Exact placement of components
• Transistor sizes
• Wire lengths, wire widths, tub boundaries.
• Any other low-level details such as parasitics..
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Stick Diagrams – Notations
Stick Diagrams – Some rules
Rule 4.
In CMOS a demarcation line is drawn to avoid
touching of p-diff with n-diff. All pMOS must lie
on one side of the line and all nMOS will have to
be on the other side.
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Stick Diagrams
How to draw Stick Diagrams
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Stick Diagrams
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Stick Diagrams
Power
A Out
Ground
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Stick Diagrams
Stick Diagrams
• Summary:
– What is stick diagram?
– Why stick diagram?
– Conventions and rules related to stick diagram.
– Drawing stick diagrams.
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Stick Diagrams
Stick Diagrams
• Home work:
1. Draw the stick diagram for two input CMOS
NAND gate.
2. Draw the stick diagram for three input NAND
gate using CMOS Logic.
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