0% found this document useful
Loading
Professional Documents
Culture Documents
Document
A1 μs 锁定时间的双环ADPLL与基于前景校准的6 ps 分辨率闪存TDC,采用180 nm CMOS: Jagdeep Kaur Sahani
Added by raisoo
Document
Synchronization - Issues - in - SDH - Networks ZH
Added by raisoo
Document
CMOS数字锁相环中的自校准技术
Added by raisoo
Document
通信学报-一种用于SDH 2Mbit - s支路输出口的全数字锁相环
Added by raisoo
Document
A - Low-Jitter - 8-GHz - RO-Based - ADPLL - With - PVT-Robust - Replica-Based - Analog - Closed - Loop - For - Supply - Noise - Compensation ZH
Added by raisoo