I/O and Interrupts

There is more variety between CPUs in the way they handle Input and Output (I/O) than in any other type of instruction. I/O processing can be either: Memory-mapped The I/O registers in the device controllers form part of regular address space, and are read and written using normal LOAD and STORE-type instructions Non-memory-mapped Special instructions (e.g. IN OUT) are used to read and write I/O registers In various combinations with the above there are four different I/O schemes in general use: Programmed I/O with busy waiting Interrupt-driven I/O DMA I/O I/O using data Channels

Programmed I/O with Busy Waiting

Used in some low-end microcomputers Single input and single output instruction Each instructions selects one I/O device (by number) and transfers a single character (byte) Example: microprocessorcontrolled video terminal Four registers: input status and character, output status and character

Programmed I/O with Busy Waiting

Whenever a character arrives from the keyboard bit 7 of the keyboard status register is set by the hardware. Input routine loops until 1 is set Whenever a character is to be displayed output routine loops until bit 7 of display status register is set to 1 by the hardware
defOutputBuffer(buffer,count): # #Outputblockofcountbytestotheterminalscreen # i=0 whilei<=count:#foreachchar: #waituntilreadythenoutput while(in(DisplayStatusReg)&0x80)==0: pass out(buffer[i]) i+=1

Interrupt-driven I/O

Primary disadvantage of programmed I/O is that CPU spends most of its time in a tight loop waiting for the device to become ready. This is called busy waiting With interrupt-driven I/O, the CPU starts the device and tells it to generate an interrupt when it is finished Done by setting interrupt-enable bit in status register Still requires an interrupt for every character read or written Interrupting a running process is an expensive business (requires saving context)

Direct Memory Access (DMA) I/O

Requires extra hardware (DMA controller chip) Chip contains (at least) four registers, all CPU (software) accessible Memory address to be read or written Count of bytes (or words) to read or write Device number or I/O address to use Read/write indicator (direction)

System with DMA controller

Direct Memory Access (DMA) I/O

To write block of 32 bytes from memory address 100 to device 4 1. CPU writes 32, 100, 4 into the first three DMA registers (memory address, count, device number) 2. CPU puts code for WRITE (say 1) into fourth (direction) DMA register, which signals DMA controller to begin operation 3. Controller reads (via bus request as CPU would) byte 100 from memory 4. Controller makes I/O request to write to device 4 5. Controller increments memory address register and decrements count register 6. Controller continues this loop until count decrements to 0 7. When count becomes 0 I/O is complete and controller asserts interrupt line on bus With DMA the CPU only has to start the I/O and respond to the final interrupt There is only one interrupt per block of bytes input or output Some DMA controllers can do two or more simultaneous I/O operations DMA process is not free when controller wants to read/write via the bus it must make the CPU wait (DMA controller always has higher priority on bus). This process is called cycle stealing DMA I/O is used on PCs and minicomputers

I/O Using Data Channels

Mainframes do enormous amounts of I/O Overhead of cycle stealing would be intolerable Solution: use special purpose I/O processors called data channels Data channel is loaded with (or pointed at) a special program and sent a start signal by the CPU When channel has completed I/O it generates an interrupt Channel has separate path to memory (memory is multiported) and therefore there is no requirement for cycle stealing Channel programs can be complex and involve transferring multiple blocks of data, therefore fewer interrupts are generated Generally two types of channel Selector channels single transfer at a time, very high speed throughput (e.g. large disk arrays) Multiplexor channels multiple low-speed devices (e.g. printers, terminals) can be handled simultaneously

I/O using data channels consists of 6 steps

I/O Using Data Channels

1. User program requests OS to perform I/O on its behalf 2. OS builds channel program in its memory to perform the I/O 3. OS executes StartIO instruction: specifies channel and device number. (After this instruction the OS can carry on with other productive work) 4. Channel fetches address of channel program 5. Each channel has a dedicated main memory address which holds this pointer 6. Channel executes channel program - this may consist of numerous instructions. 7. Channel instruction has an opcode (write, read, control, sense, jump, etc.) address of main memory buffer for data, miscellaneous bits and a byte count for the I/O 8. When I/O has completed, channel asserts the interrupt line to notify the CPU

I/O: Two Examples

Above is a typical DEC PDP-8 mincomputer configuration from the late 1960s Below an IBM 370 mainframe from the early 1970s. Note the dualported memory and data channels

General principles for interrupt handling are applicable to every method of I/O except programmed with busy waiting It is important that interrupts are handled transparently, i.e. programs which are interrupted by (another program's) I/O termination carry on after the interrupt as if nothing had happened There are two sides to interrupt handling: hardware and software Hardware 1. Device controller asserts interrupt line on the bus 2. When the CPU is ready for interrupt (it cannot pause during an instruction) it asserts interrupt acknowledge on the bus 3. When the device controller sees the acknowledgement, it puts an interrupt number on the bus to identify itself 4. CPU removes the interrupt number from the bus and stores it in a temporary register 5. CPU pushes PC and PSW onto stack in order to save return address to program being interrupted PC: program counter (aka Instruction Counter or - to Intel - Instruction Pointer PSW: (Program Status Word - essentially the flags register, although some manufacturers include the PC in the PSW) 6. CPU locates Interrupt Service Routine (ISR) by indexing into Interrupt Vectors an array held at the bottom of main memory. This is done by multiplying the interrupt number, n, by the size of a procedure pointer (i.e. address in main memory of an instruction) Software ISR saves all registers. (This is called saving the context of the interrupted program) ISR determines which device caused the interrupt. (This is usually done by reading a specific register in the device controller - disk controllers often have more than one disk attached, for example) ISR handles any error which may have occurred ISR updates program-accessible information about the I/O which has just terminated (character count read, for example) If necessary ISR asserts an interrupt handling completed signal (the 8559A chip used on PCs requires this) ISR restores saved registers ISR executes RETURN FROM INTERRUPT instruction, passing control back to the interrupted program

Interrupts and Faults

Nested Interrupts

It is quite possible, even likely, that on a multi-user or multidevice machine an interrupt will occur while a previous interrupt is being handled Two possible approaches Postpone servicing of new interrupt until old ISR has finished Achieved by disabling interrupts for the duration of the ISR Advantage: simpler code Disadvantage: some devices simply cannot be made to wait. A serial line running at 9600bps will deliver a character every 1042 usec, if the ISR disables interrupts for longer than this period, then characters can be lost Allow ISR's to be interrupted, but only by interrupts of a higher priority Achieved by masking off interrupts of a lower priority than the current one, and allowing for ISR's to be suspended, i.e. have their contexts saved Advantage: no data loss Disadvantage: more complex code In general (with the exception of low-end machines) the latter approach is taken

Nested Interrupts

1. 2. 3. 4. 5.

User program running when printer interrupt (priority level 2) occurs User context saved onto stack, printer ISR runs RS232C interrupt (priority level 5) occurs Printer ISR context saved onto stack, RS232C ISR runs Disk interrupt (priority level 4) occurs current ISR priority higher, so interrupt held pending 6. RS232C ISR terminates, printer ISR resumes but disk interrupt is immediately allowed, printer context resaved, and disk ISR runs 7. Disk ISR terminates, allowing printer ISR to resume 8. Printer ISR terminates, user program resumes

Faults (or traps) are caused by a program attempting to do something which it either cannot or may not: the impossible or the illegal. Examples: Impossible Execute something which is not an instruction (illegal opcode), divide by zero, reference non-existent memory Illegal Execute a privileged instruction (IN, OUT, StartIO, load alarm clock register), reference memory outside the program's limits Some of these will be recognised during the decode stage, some in the operand fetch stage, some in the execute stage The cpu's response is the same: each fault has a fault number associated with it and this number is used to index into into the fault vectors and transfer control to a fault handing routine. Unlike interrupts - which are outside the program's control and caused by other programs - faults are events which usually cause the program to be terminated and thus the fault service routine will not, unlike the ISR, return control the the faulting program One exception to this is instructions which use the faulting mechanism to request services from the operating system, known as system calls. These instructions give controlled access to system functionality and will (with the exception of a program termination function) always return control to the user program, unless the instruction has been used incorrectly It is perhaps unfortunate that some CPU manufacturers have combined the interrupt and fault vectors and called them all interrupts - including, in the case of Intel, the system call instruction (INT) itself. This - like Intel's bizarre use of segmentation in the x86 - has caused serious confusion of terminology.

Faults