Welcome to Scribd. Sign in or start your free trial to enjoy unlimited e-books, audiobooks & documents.Find out more
Download
Standard view
Full view
of .
Look up keyword
Like this
23Activity
0 of .
Results for:
No results containing your search query
P. 1
Datasheet 74192

Datasheet 74192

Ratings:

4.67

(1)
|Views: 4,901|Likes:
Published by phongbui135

More info:

Published by: phongbui135 on Apr 30, 2009
Copyright:Attribution Non-commercial

Availability:

Read on Scribd mobile: iPhone, iPad and Android.
download as PDF, TXT or read online from Scribd
See more
See less

08/19/2013

pdf

text

original

 
5-1FAST AND LS TTL DATA
PRESETTABLE BCD/DECADEUP/DOWN COUNTERPRESETTABLE 4-BIT BINARYUP/DOWN COUNTER
The SN54/74LS192 is an UP/DOWN BCD Decade (8421) Counter and theSN54/74LS193 is an UP/DOWN MODULO-16 Binary Counter. SeparateCount Up and Count Down Clocks are used and in either counting mode thecircuits operate synchronously. The outputs change state synchronous withthe LOW-to-HIGH transitions on the clock inputs.Separate Terminal Count Up and Terminal Count Down outputs areprovided which are used as the clocks for a subsequent stages without extralogic, thus simplifying multistage counter designs. Individual preset inputsallow the circuits to be used as programmable counters. Both the ParallelLoad (PL) and the Master Reset (MR) inputs asynchronously override theclocks.
Low Power ...95 mW Typical Dissipation
High Speed...40 MHz Typical Count Frequency
Synchronous Counting
Asynchronous Master Reset and Parallel Load
Individual Preset Inputs
Cascading Circuitry Internally Provided
Input Clamp Diodes Limit High Speed Termination Effects
NOTE:The Flatpak versionhas the same pinouts(Connection Diagram) asthe Dual In-Line Package.
CONNECTION DIAGRAM DIP
(TOP VIEW)
14131211109123456716158VCCP1P0MRTCDTCUP2PLP3Q1Q0CPDCPUQ2Q3GND
PIN NAMESLOADING
(Note a)HIGHLOWCPUCPDMRPLPnQnTCDTCUCount Up Clock Pulse InputCount Down Clock Pulse InputAsynchronous Master Reset (Clear) InputAsynchronous Parallel Load (Active LOW) InputParallel Data InputsFlip-Flop Outputs (Note b)Terminal Count Down (Borrow) Output (Note b)Terminal Count Up (Carry) Output (Note b)0.5 U.L.0.5 U.L.0.5 U.L.0.5 U.L.0.5 U.L.10 U.L.10 U.L.10 U.L.0.25 U.L.0.25 U.L.0.25 U.L.0.25 U.L.0.25 U.L.5 (2.5) U.L.5 (2.5) U.L.5 (2.5) U.L.
NOTES:a. 1 TTL Unit Load (U.L.) = 40
µ
A HIGH/1.6 mA LOW.b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)b.Temperature Ranges.
SN54/74LS192SN54/74LS193
PRESETTABLE BCD/DECADEUP/DOWN COUNTERPRESETTABLE 4-BIT BINARYUP/DOWN COUNTER
LOW POWER SCHOTTKY
J SUFFIX
CERAMICCASE 620-09
N SUFFIX
PLASTICCASE 648-08
161161
ORDERING INFORMATION
SN54LSXXXJCeramicSN74LSXXXNPlasticSN74LSXXXDSOIC
161
D SUFFIX
SOICCASE 751B-03
LOGIC SYMBOL
VCC= PIN 16GND = PIN 85432671291011511 CPDQ0Q1Q2Q3TCDP3P2P1P0PLCPUTCU13MR14
 
5-2FAST AND LS TTL DATA
SN54/74LS192
SN54/74LS193
STATE DIAGRAMSLS192 LOGIC EQUATIONSFOR TERMINAL COUNTLS192LS193
COUNT UPCOUNT DOWN0123456789101112 1314150123456789101112 131415
TCU= Q0 
Q3 
CPUTCD= Q0 
Q1 
Q2 
Q3 
CPD
LS193 LOGIC EQUATIONSFOR TERMINAL COUNT
TCU= Q0 
Q1
Q2
Q3 
CPUTCD= Q0 
Q1 
Q2 
Q3 
CPD
LOGIC DIAGRAMS
VCC= PIN 16GND = PIN 8= PIN NUMBERS
LS192
P0P1P2P3TCU(CARRYOUTPUT)Q0Q1Q2Q3MR(CLEAR)(DOWNCOUNT)CPD(UP COUNT)CPU(LOAD)PL
12673459111210131514
TCD(BORROWOUTPUT)
SDQQCDTSDQQCDTSDQQCDTSDQQCDT
 
5-3FAST AND LS TTL DATA
SN54/74LS192
SN54/74LS193
LOGIC DIAGRAMS (continued)
VCC= PIN 16GND = PIN 8= PIN NUMBERS
LS193
P0P1P2P3Q0Q1Q2Q3MR(CLEAR)(DOWNCOUNT)CPD(UP COUNT)CPU(LOAD)PL
12673459111210131514SDQQCDTSDQQCDTSDQQCDTSDQQCDT
TCU(CARRYOUTPUT)TCD(BORROWOUTPUT)

Activity (23)

You've already reviewed this. Edit your review.
1 hundred reads
1 thousand reads
Camilo Valencia liked this
Mf Ramirez Abreo liked this
tanujchawla30 liked this
Lulu Poveda liked this
freud1 liked this

You're Reading a Free Preview

Download
scribd
/*********** DO NOT ALTER ANYTHING BELOW THIS LINE ! ************/ var s_code=s.t();if(s_code)document.write(s_code)//-->