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Chng 5: Ngn ng m t phn
cng VHDL
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I. INTRODUCTION
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VHDL = VHSIC Hardware Description
Language
(VHSIC = Very High Speed Integrated Circuit)
VHDL is a hardware description language. It describes
the behavior of an electronic circuit or system, from
which the physical circuit or system can then be
attained.
VHDL was the original and rst hardware description
language to be standardized by the Institute of
Electrical and Electronics Engineers
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II. CODE STRUCTURE
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1. Fundamental VHDL Units
A standalone piece of VHDL code is composed of at least
three fundamental sections:
LIBRARY declarations: Contains a list of all libraries to
be used in the design.
ENTITY: Species the I/O pins of the circuit.
ARCHITECTURE: Contains the VHDL code proper,
which describes how the circuit should behave
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Fundamental sections of a VHDL code
2. Library Declarations
To declare a LIBRARY two lines of code are needed, one
containing the name of the library
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EX:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
Using std_logic_1164 package from the ieee library
EX:
LIBRARY std;
USE std.standard.all;
Using standard package from the std library
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The ieee library contains several packages below:
(ieee = Institute of Electrical and Electronics Engineers)
std_logic_1164: Specifies the STD_LOGIC (8 levels)
and STD_ULOGIC (9 levels) multi-valued logic
systems.
std_logic_arith: Specifies the SIGNED and
UNSIGNED data types and related arithmetic and
comparison operations.
std_logic_signed: Contains functions that allow
operations with STD_LOGIC_VECTOR data to be
performed as if the data were of type SIGNED.
std_logic_unsigned: Contains functions that allow
operations with STD_LOGIC_VECTOR data to be
performed as if the data were of type UNSIGNED
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3. ENTITY
An ENTITY is a list with specications of all input and out
put pins (PORTS) of the circuit
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3 ENTITY (tt)
The mode of the signal can be IN, OUT, INOUT, or
BUFFER.
The type of the signal can be BIT, STD_LOGIC,
INTEGER,..
the name of the entity can be basically any name,
except VHDL reserved words
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Example: entity of the NAND gate
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Example: entity of the D Flip Flop
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Example: entity of the Mux
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ENTITY mux IS
PORT (a, b : IN std_logic_vector (7 downto 0);
sel : IN std_logic_vector (0 to 1);
c: OUT std_logic_vector (7 downto 0));
END mux;
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4. ARCHITECTURE
The ARCHITECTURE is a description of how the
circuit should behave . Its syntax is the following:
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4. ARCHITECTURE (tt)
A declarative part: Signals and constants are declared
The code part: Like in the case of an entity
The name of an architecture can be basically any
Name (except VHDL reserved words) , including the
same name as the entitys.
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Example : architecture of the NAND gate again.
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III. DATATYPES
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1. Signal
- Signal, which represents interconnection wires that
connect component instantiation ports together.
- Signals can be declared in entity declaration
sections, architecture declarations, and package
declarations
- A signal declaration looks like this:
SIGNAL signal_name : signal_type [:= initial_value];
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2. Variables
- Variables are used for local storage in process statements
and subprograms. As opposed to signals, which have
their values scheduled in the future, all assignments to
variables occur immediately.
- A variable declaration looks like this:
VARIABLE variable_name : variable_type[:= value];
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Reference from : http://www.edaboard.com/thread19065.html
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ENTITY mux IS
PORT (i0, i1, i2, i3, a, b : IN
std_logic;
q : OUT std_logic);
END mux;
ARCHITECTURE wrong of mux IS
SIGNAL muxval : INTEGER;
BEGIN
PROCESS ( i0, i1, i2, i3, a, b )
BEGIN
muxval <= 0;
IF (a = 1) THEN
muxval <= muxval + 1;
END IF;
IF (b = 1) THEN
muxval <= muxval + 2;
END IF;
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CASE muxval IS
WHEN 0 =>
q <= I0 AFTER 10 ns;
WHEN 1 =>
q <= I1 AFTER 10 ns;
WHEN 2 =>
q <= I2 AFTER 10 ns;
WHEN 3 =>
q <= I3 AFTER 10 ns;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS;
END wrong;
Incorrect Mux Example
ENTITY mux IS
PORT (i0, i1, i2, i3, a, b : IN
std_logic;
q : OUT std_logic);
END mux;
ARCHITECTURE wrong of mux IS
VARIABLE muxval : INTEGER;
BEGIN
PROCESS ( i0, i1, i2, i3, a, b )
BEGIN
muxval := 0;
IF (a = 1) THEN
muxval := muxval + 1;
END IF;
IF (b = 1) THEN
muxval := muxval + 2;
END IF; 24
CASE muxval IS
WHEN 0 =>
q <= I0 AFTER 10 ns;
WHEN 1 =>
q <= I1 AFTER 10 ns;
WHEN 2 =>
q <= I2 AFTER 10 ns;
WHEN 3 =>
q <= I3 AFTER 10 ns;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS;
END wrong;
correct Mux Example
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3. Constants
- Constant objects are names assigned to specific
values of a type
- A constant declaration looks like this:
CONSTANT constant_name : type_name[:= value];
EX:
CONSTANT PI: REAL := 3.1414;
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4. Pre-Dened DataTypes
a. BIT (and BIT_VECTOR): 2-level logic 0, 1
Examples:
SIGNAL x : BIT;
x <= 1;
--x is declared as a one-digit signal of type BIT.
SIGNAL y : BIT_VECTOR (3 DOWN TO 0);
y <= 1100
--y is a 4-bit vector , with the left most bit being the MSB.
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b. STD_LOGIC (and STD_LOGIC_VECTOR):
8-valued logic system introduced in the IEEE1164 standard.
X Forcing Unknown
0 Forcing Low
1 Forcing High
Z High impedance
W Weak unknown
L Weak low
H Weak high
Dont care
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Examples:
SIGNAL x: STD_LOGIC;
-- x is declared as a one-digit signal of type STD_LOGIC.
SIGNAL y: STD_LOGIC_VECTOR (3 DOWNTO 0)
-- y is declared as a 4-bit vector, with the leftmost bit being
the MSB.
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c. INTEGER TYPES
INTEGER TYPES are exactly like mathematical integers.
All of the normal predefined mathematical functions like
add, subtract, multiply, and divide apply to integer types
the integer range is specified from -2,147,483,647 to
2,147,483,647
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Examples:
ARCHITECTURE test OF test IS
BEGIN
PROCESS(X)
VARIABLE a : INTEGER;
VARIABLE b : real;
BEGIN
a := 1; --Ok
a := -1; --Ok
a := 1.5; --error
END PROCESS;
END test;
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e. REAL TYPES
Real types are used to declare objects that emulate
mathematical real numbers. They can be used to
represent numbers out of the range of integer
values as well as fractional values
Real numbers ranging from -1.0E38 to +1.0E38.
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5. PHYSICAL TYPES
Physical types are used to represent physical quantities
such as distance, current, time, and so on.
A physical type provides for a base unit, and successive
units are then defined in terms of this unit. The
smallest unit representable is one base unit; the largest
is determined by the range specified in the physical
type declaration
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Ex:
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SUMMARY:
BOOLEAN: True, False.
INTEGER: 32-bit integers (from -2,147,483,647 to
+2,147,483,647).
NATURAL: Non-negative integers (from 0 to
+2,147,483,647).
REAL: Real numbers ranging from -1.0E38 to
+1.0E38.
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6. User-Defined Data Types
VHDL allows the user to define his/her own data types. It
calls User-defined integer type
Ex1:
TYPE integer IS RANGE -2147483647 TO +2147483647;
-- This is indeed the pre-defined type INTEGER.
TYPE my_integer IS RANGE -32 TO 32;
-- A user-defined subset of integers
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6. User-Defined Data Types (tt)
Ex2:
TYPE bit IS ('0', '1');
-- This is indeed the pre-defined type BIT
TYPE my_logic IS ('0', '1', 'Z');
-- A user-defined subset of std_logic.
Ex 3:
TYPE state IS (idle, forward, backward, stop);
-- An enumerated data type, typical of finite state machines.
TYPE color IS (red, green, blue, white);
-- An enumerated data type.
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7. Arrays
Array types group one or more elements of the same type
together as a single object. Arrays can be one-dimensional
(1D), two-dimensional (2D)
The pre-defined synthesizable types in each of these
categories are the following:
- Scalars: BIT, STD_LOGIC, STD_ULOGIC, and
BOOLEAN.
- Vectors: BIT_VECTOR, STD_LOGIC_VECTOR,
STD_ULOGIC_VECTOR, INTEGER, SIGNED, and
UNSIGNED.
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Example:
-- 1D array
TYPE row IS ARRAY (7 DOWNTO 0) OF STD_LOGIC;
-- 1Dx1D array
TYPE matrix IS ARRAY (0 TO 3) OF row;
.
SIGNAL y: row;
SIGNAL x: matrix;
.
y := 11110000 -- OK
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IV. OPERATORS AND ATTRIBUTES
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1. Assignment Operators
<= Used to assign a value to a SIGNAL.
:= Used to assign a value to a VARIABLE, CONSTANT,
or GENERIC. Used also for establishing initial values.
=> Used to assign values to individual vector elements
or with OTHERS.
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Example:
SIGNAL x : STD_LOGIC;
VARIABLE y : STD_LOGIC_VECTOR(3 DOWNTO 0);
-- Leftmost bit is MSB
SIGNAL w: STD_LOGIC_VECTOR(0 TO 7);
-- Rightmost bit is MSB
Then the following assignments are legal:
x <= '1';
y := "0000";
w <= "10000000";
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2. Logical Operators
The logical operators are:
NOT, AND, OR, NAND, NOR, XOR, XNOR
The data must be of type BIT, STD_LOGIC,
STD_ULOGIC,BIT_VECTOR,STD_LOGIC_VECTOR,
STD_ULOGIC_VECTOR
Examples:
y <= NOT a AND b; -- (a'.b)
y <= NOT (a AND b); -- (a.b)'
y <= a NAND b; -- (a.b)'
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3. Arithmetic Operators
Used to perform arithmetic operations. The data
can be of type INTEGER, SIGNED, UNSIGNED, or
REAL
If the std_logic_signed or the std_logic_unsigned
package of the ieee library is used, then
STD_LOGIC_VECTOR can also be employed
directly in addition and subtraction operations
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+ Addition
- Subtraction
* Multiplication
/ Division
** Exponentiation
MOD Modulus
REM Remainder
ABS Absolute value
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4. Comparison Operators
Used for making comparisons. The data can be of any
of the types listed above. The relational operators are:
= Equal to
/= Not equal to
< Less than
> Greater than
<= Less than or equal to
>= Greater than or equal to Shift Operators
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6. Data Attributes
dLOW: Returns lower array index
dHIGH: Returns upper array index
dLEFT: Returns leftmost array index
dRIGHT: Returns rightmost array index
dLENGTH: Returns vector size
dRANGE: Returns vector range
dREVERSE_RANGE: Returns vector range in reverse order
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dVAL(pos): Returns value in the position specified
dPOS(value): Returns position of the value specified
dLEFTOF(value): Returns value in the position to
the left of the value specified
dVAL(row, column): Returns value in the position
specified
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Example: Consider the following signal:
SIGNAL d : STD_LOGIC_VECTOR (7 DOWNTO 0);
Then:
d'LOW=0, d'HIGH=7
d'LEFT=7, d'RIGHT=0
d'LENGTH=8,
d'RANGE = (7 downto 0),
d'REVERSE_RANGE = (0 to 7).
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7. Signal Attributes
sEVENT: Returns true when an event occurs on s
sSTABLE: Returns true if no event has occurred on s
sACTIVE: Returns true if s = 1
sQUIET <time>: Returns true if no event has occurred
during the time specified
sLAST_EVENT: Returns the time elapsed since last event
sLAST_ACTIVE: Returns the time elapsed since last s = 1
sLAST_VALUE: Returns the value of s before the last
event
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Ex:
IF (clk'EVENT AND clk='1')... -- EVENT attribute used
with IF
IF (NOT clk'STABLE AND clk='1')... -- STABLE attribute
used with IF
WAIT UNTIL (clk'EVENT AND clk='1'); -- EVENT attribute
used with WAIT
IF RISING_EDGE(clk)... -- call to a function
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8. GENERIC
GENERIC is a way of specifying a generic parameter
(that is,a static parameter that can be easily modified
and adapted to diferent applications).The purpose is to
confer the code more flexibility and reusability.
A GENERIC statement must be declared in the
ENTITY. Its syntax is shown below:
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Ex:
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Ex: write code for the fulladd 2 bit
library ieee;
use ieee.std_logic_1164.all;
entity fulladd is
generic (n : integer := 2);
-------thay doi n de thay doi so bit cho fulladd---------------
port (a,b: in std_logic_vector (n -1 downto 0);
cin : in std_logic;
s : out std_logic_vector (n -1 downto 0);
cout : out std_logic);
end fulladd;
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architecture myfulladd of fulladd is
begin
process (a,b,cin)
variable carry : std_logic_vector (n downto 0);
begin
carry (0) := cin;
for i in 0 to (n -1) loop
s(i) <= a(i) xor b(i) xor carry (i);
carry(i+1) := (a(i) and b(i)) or (a(i) and
carry(i))or (b(i)and carry(i));
end loop;
cout <= carry(n);
end process;
end myfulladd; 55
V. Concurrent Code
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1 Combinational versus Sequential Logic
Combinational logic is that in which the output of
the circuit depends solely on the current inputs
Sequential logic is defined as that in which the
output does depend on previous inputs storage
elements are required, which are connected to the
combinational logic block through a feedback loop
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2. Concurrent vs Sequential Code
VHDL code is inherently concurrent (parallel). Only
statements placed inside a PROCESS, FUNCTION, or
PROCEDURE are sequential.
In general we can only build combinational logic
circuits with concurrent code.
To obtain sequential logic circuits, sequential code
must be employed. Indeed, with the latter we can
implement both, sequential as well as combinational
circuits.
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3. Concurrent code
In summary, in concurrent code the following can be
used:
Operators;
The WHEN statement:
(WHEN/ELSE or WITH/SELECT/WHEN);
The GENERATE statement;
The BLOCK statement.
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4. Operators.
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Ex:
y<= (a and b) or c;
y <= a and (b or c);
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Y
a
b
c
Y
c
b
a
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f
x
3
x
1
x
2 A
B
Library ieee;
Use IEEE.std_logic_1164.all;
Entity example1 IS
END example1;
ARCHITECTURE Lfun of example1 is
Signal A,B : std_logic;
BEGIN
END Lfun;
f<= A OR B;
A<= (x1 AND x2) ;
B<= (NOT x2 AND x3);
A<= (x1 AND x2) ;
f<= A OR B;
B<= (NOT x2 AND x3);
A<= (x1 AND x2) ;
B<= (NOT x2 AND x3);
f<= A OR B;
PORT (x1,x2,x3: IN std_logic;
f : OUT std_logic);
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Example: Mux 4 to 1
---------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
---------------------------------------
ENTITY mux IS
PORT ( a, b, c, d, s0, s1: IN STD_LOGIC;
y: OUT STD_LOGIC);
END mux;
---------------------------------------
ARCHITECTURE pure_logic OF mux IS
BEGIN
y <= (a AND NOT s1 AND NOT s0) OR
(b AND NOT s1 AND s0) OR
(c AND s1 AND NOT s0) OR
(d AND s1 AND s0);
END pure_logic;
----------------------------------------
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Simulation results of example
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The signal is assigned a value based on a condition.
signal_name <= value_1 when condition1 else
value_2 when condition2 else
value_3 when condition3 else

value_n;
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5. When else Statements
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Ex: Mux 4 to1
Two solutions are presented:
Solution 1: WHEN/ELSE
Solution 2: WITH/SELECT/WHEN
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6. with-select-when Statements
Syntax is:
with select_signal select
signal_name <= value1 when value1_of_select_sig,
value2 when value2_of_select_sig,
value3 when value3_of_select_sig,
value_default when others;
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Ex 2 : design Encoder 8 3 use
with select when
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Ex 3: design ALU
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Exercise 1 :
design a decoder 3 8 use when else
Exercise 2:
Design a binary decoder for common anode led
Input: BCD (binary coded decimal)
Output: seven segment code (a is MSB)

..\..\..\baitapvhdl\BCD_TO_LED7SEG\BCD_TO_LED7
EG.qpf
Bi tp: vit chng trnh chy m phng b alu 2 bit c
bng trng thi nh sau:
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Ket qua:
..\..\..\baitapvhdl\alu\alu.qpf
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6. GENERATE
GENERATE is another concurrent statement. It allows a
section of code to be repeated a number of times.
FOR / GENERATE:
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EX:
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VI. SEQUENTIAL CODE
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1. PROCESS
A PROCESS is a sequential section of VHDL code. It is
characterized by the presence of IF, WAIT, CASE, or
LOOP, and by a sensitivity list. A PROCESS must be
installed in the main code, and is executed every time a
signal in the sensitivity list changes.
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Syntax of PROCESS:
VARIABLES are optional. If used, they must be declared in
the declarative part of the PROCESS. The initial value is
not synthesizable, being only taken into consideration in
simulations.
2. IF
IF, WAIT, CASE, and LOOP are the statements intended for
sequential code. Therefore, they can only be used inside a
PROCESS, FUNCTION, or ROCEDURE.
The syntax of IF is shown below:
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Example 1: Design Combinational logic
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Example 2: Design Combinational logic
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Exercise 3: write code for the circuit below
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LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mux IS
PORT ( a,b : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
c : OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END mux;
ARCHITECTURE example OF mux IS
BEGIN
PROCESS (a, b, sel)
BEGIN
IF (sel = "00") THEN
c <= "00000000";
ELSIF (sel=01) THEN
c <= a;
ELSIF (sel = "10") THEN
c <= b;
ELSE
c <= ZZZZZZZZ;
END IF;
END PROCESS;
END example;
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Example 4:
Design a DFF with Asynchronous Reset, triggered at
the rising-edge of (clk).
When Rst =1, the output = 0, regardless of clk.
Otherwise, the output = d when clk changes from 0 to 1
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Exercise 1: write code for the circuit below
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ENTITY example IS
PORT ( a, b, clk: IN BIT;
q: OUT BIT);
END example;
---------------------------------------
ARCHITECTURE example OF example IS
SIGNAL temp : BIT;
BEGIN
temp <= a NAND b;
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk='1') THEN q<=temp;
END IF;
END PROCESS;
END example;
---------------------------------------
Exercise 2 : Design One-digit Counter
The code below implements a progressive 1-digit
decimal counter (0 9 0). It contains a single-bit
input (clk) and a 4-bit output (digit)
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4. Case
CASE signal X IS
when value_1 =>
statements A ;
when value_2 =>
statements B ;
:
when others =>
statements P ;
END CASE;
Value_1
Value_2
Statements A
Statements B
Statements A
NO
NO
yes
yes
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Example 1: design Decoder 2 4
case A is
when 00 => y <= 0111 ;
when 01 => y <= 1011 ;
when 10 => y <= 1101 ;
when 11 => y <= 1110 ;
when others => y <= 1111 ;
end case;
Example 2: Design Two-digit Counter with SSD Output
The code below implements a progressive 2-digit
decimal counter (0 99 0), with external asynchronous
reset plus binary-coded decimal (BCD) to seven-segment
display (SSD) conversion. Diagrams of the circuit and SSD
are shown in figure below
Notice that we have chosen the following connection
between the circuit and the SSD: xabcdefg (that is, the MSB
feeds the decimal point, while the LSB feeds segment g).
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Code VHDL dem 2 digit.pdf
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Design a Two-digit Counter (00 12)
Exercise 2:
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Exercise 1
Design a Two-digit Counter (00 24), using decoder
BCD to led 7 segment
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Counter
00 - 24
74LS47
74LS47
ck
Digit 2
Digit 1
RESET
Exercise 3: Design Comparator 8 bit
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5. WAIT
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WAIT UNTIL
The WAIT UNTIL statement accepts only one signal.
Since the PROCESS has no sensitivity list in this case, WAIT
UNTIL must be the first statement in the PROCESS. The
PROCESS will be executed every time the condition is met.
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105
WAIT ON
WAIT ON, on the other hand, accepts multiple
signals. The PROCESS is put on hold until any of the
signals listed changes. In the example below, the
PROCESS will continue execution whenever a change
in rst or clk occurs.
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Example: 8-bit register with asynchronous reset
PROCESS
BEGIN
WAIT ON clk, rst;
IF (rst='1') THEN
output <= "00000000";
ELSIF (clk'EVENT AND clk='1') THEN
output <= input;
END IF;
END PROCESS;
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Example : DFF with Asynchronous Reset
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6. LOOP
The LOOP is useful when a piece of code must be
instantiated several times. Like IF, WAIT, and CASE,
LOOP is intended exclusively for sequential code, so it
too can only be used inside a PROCESS, FUNCTION, or
PROCEDURE.
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FOR / LOOP
The loop is repeated a fixed number of times
The syntaxes below:
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WHILE / LOOP
The loop is repeated until a condition no longer holds
The syntaxes below:
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Example 1: Design Carry Ripple Adder 8 bit
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a
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Example 2 : design a FSM
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Example 3 : design a FSM
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Ex: Traffic Light Controller
Link to Chapter 8 (State Machines/page 186)
MIT.Press,.Circuit.Design.with.VHDL.(2004).TLF_UnEn
crypted.pdf
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VI. PACKAGES AND
COMPONENTS
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Fundamental units of VHDL code.
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1. Component
A COMPONENT is simply a piece of conventional code .
However, by declaring such code as being a COMPONENT,
it can then be used within another circuit, thus allowing
the construction of hierarchical designs.
A COMPONENT is also another way of partitioning a code
and providing code sharing and code reuse.
example:
ip-ops, multi-plexers, adders, basic gates, etc..
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COMPONENT declaration:
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COMPONENT instantiation:
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Ex:
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Example: Write code for the circuit below
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2. PACKAGES
A package is a collection of types, constants, subprograms
and possibly other things, usually intended to implement
some particular service or to isolate a group of related
items.
A package may be split into two parts: a package
declaration, which defines its interface, and a package
body, which defines the deferred details. The body part
may be omitted if there are no deferred details
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The syntax for a package is:
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Example:
Example: design the boolean function using package
and component, y = a.b + a.b
---- cong dao (not)------
library ieee;
use ieee.std_logic_1164.all;
entity congdao is
port (a : in std_logic; b : out std_logic);
end congdao;
architecture mycongdao of congdao is
begin
b <= not a;
end mycongdao;
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----- cong and ------
library ieee;
use ieee.std_logic_1164.all;
entity congand is
port (a,b : in std_logic; c : out std_logic);
end congand;
architecture mycongand of congand is
begin
c <= a and b;
end mycongand;
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---------------- cong or ---------------
library ieee;
use ieee.std_logic_1164.all;
entity congor is
port (a,b : in std_logic; c : out std_logic);
end congor;
architecture mycongor of congor is
begin
c <= a or b;
end mycongor;
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---- khai bao component ----
----trong package -------------
library ieee;
use ieee.std_logic_1164.all;
package mycomponent is
component congdao is
port (a: in std_logic;
b : out std_logic);
end component;
component congand is
port (a,b : in std_logic;
c : out std_logic);
end component;
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component congor is
port (a,b : in std_logic;
c : out std_logic);
end component;
end mycomponent;
----top module------
library ieee;
use ieee.std_logic_1164.all;
use work.mycomponent.all;
entity mypackage is
port (a,b : in std_logic;
y : out std_logic);
end mypackage;
architecture mypackage of
mypackage is
signal d1,d2,d3,d4 : std_logic;
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begin
u1 : congdao port map (a,d1);
u2 : congand port map (d1,b,d3);
u3 : congdao port map (b,d2);
u4 : congand port map (a,d2,d4);
u5 : congor port map (d3,d4,y);
end mypackage;
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exercise 1: Design combinational circuit
exercise 2: Design A 16-to-1 mux using 4-to-1 mux
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THANK YOU!
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