Henry W.

Ott
HOC
ELECTROMAGNETIC
COMPATIBILITY
EMC ASPECTS OF FUTURE
HIGH SPEED DIGITAL DESIGNS
OOOO1
2000
By
Henry W. Ott
Henry Ott Consultants
Livingston, NJ 07039
(973) 992-1793
www.hottconsultants.com hott@ieee.org
PCB Design Conference - East
Keynote Address
September 12, 2000
Henry W. Ott
HOC
ELECTROMAGNETIC
COMPATIBILITY
ELECTROMAGNETIC COMPATABILITY
DRIVING FORCES
SYS - 01008
2000
EMC
Regulations
Technology
Signal
Integrity
Time to
Market
Henry W. Ott
HOC
ELECTROMAGNETIC
COMPATIBILITY
DIFFERENTIAL - MODE RADIATION
DIG 00269
Signal
Ground
I
PCB
1998
R
a
d
ia
te
d
Emission
E = K
1
f
2
AI
0
Henry W. Ott
HOC
ELECTROMAGNETIC
COMPATIBILITY
CONTROLLING DIFFERENTIAL-MODE EMISSIONS
! Reduce Loop Area
PCB Technology Has Not Keep Up With
the Increase in Frequency Squared
! Cancellation Techniques
Canceling Clock Loops
Multiple Decoupling Capacitors
! Spread Spectrum Techniques
Clock Dithering
ADIG - 01028
2000
Henry W. Ott
HOC
ELECTROMAGNETIC
COMPATIBILITY
DIG - 01013
2000
Clockwise Loop Counter-Clockwise Loop
C
C IC
Clock
Gnd
Gnd
CCW
CW
CANCELLATION TECHNIQUES
Henry W. Ott
HOC
ELECTROMAGNETIC
COMPATIBILITY
COMMON-MODE RADIATION
DIG 00268
Gnd Plane
Or Grid
VN
PWB
Icm
I/O Cable
Gnd Wire
Icm
Cable
Equivalent Circuit
VN
1998
E=K2fLIcm
Henry W. Ott
HOC
ELECTROMAGNETIC
COMPATIBILITY
SKIN EFFECT
! Due to the Skin Effect, High Frequency Currents Can Only
Penetrate a Metal a Very Small Distance
! Therefore, at High Frequencies all Currents are on the Surface
of Conductors, and Cannot Penetrate them.
PCB - 01013
1996
Henry W. Ott
HOC
ELECTROMAGNETIC
COMPATIBILITY
GROUND RETURN CURRENTS
! Return Currents Will Always Flow on the Nearest Plane
! The Top and Bottom Surfaces of a Plane Act as Separate
Conductors
! If The Top and Bottom Surfaces of a Plane Are Used for the
Return Current,
How Does the Return Current Get From the Top to the
Bottom of the Plane?
! If a Mixture of Power and Ground Planes are Used for the
Return Current,
How Does the Return Current Get From One Plane to the
Other?
PCB - 01022A
1996
Henry W. Ott
HOC
ELECTROMAGNETIC
COMPATIBILITY
GROUND CURRENT FLOW
PCB - 01049
1999
Plane
Signal
Layer
Signal
Layer
Plane 1
Signal
Layer
Signal
Layer
Plane 2
?
Signal Traces Adjacent to the Same Plane Signal Traces Adjacent to Different Planes
OK
A Problem Unless We
Do Something
Via
Via
Henry W. Ott
HOC
ELECTROMAGNETIC
COMPATIBILITY
HIGH SPEED CLOCK ROUTING GUIDELINES
(in order of preference)
! Route Clock on One Layer Adjacent to a Plane
! Route Clock on Two Layers, Adjacent to the Same Plane
! Route Clock on Two Layers, Adjacent to Two Planes of the
Same Type (i.e., Ground or Power) and Connect Planes
Together With a Via Wherever there is a Signal Via
! Route Clock on Two Layers, Adjacent to Two Different Types of
Planes (i.e., Ground and Power) and Connect Planes Together
With a Decoupling Capacitor Wherever There is a Signal Via
PCB - 01044
1998
Henry W. Ott
HOC
ELECTROMAGNETIC
COMPATIBILITY
SLOT INDUCED GROUND PLANE VOLTAGE DROP
(3 nS RISE-TIME SQUARE WAVE)
MEA - 00204X
1996
Notes:
G Slot is 0.025 Wide.
G Signal Trace Width is 0.050.
G Holes = A Pattern of Fifteen 0.052 Diam.
Holes Along a 1 Line
l ll l V
AB
dB
0 in 15 mV
in 20 mV 2.5
in 26 mV 4.8
1 in 49 mV 10.3
1 in 75 mV 14.0
Holes 15+ mV
B A
Via Via
1
3
Ground
Plane
l ll l
Trace on Opposite
Side of Board
Henry W. Ott
HOC
ELECTROMAGNETIC
COMPATIBILITY
We Must Learn To Ask The Question,
Where Does The Return Current Flow?
GRD - 01020
1999
Henry W. Ott
HOC
ELECTROMAGNETIC
COMPATIBILITY
MEA - 00216X
1994
Ground Plane Current Distribution
I
Via
Ground Plane
Constriction of
Current, High
Inductance
Current Spreads Out, Low Inductance
Constriction of
Current, High
Inductance
Trace on Opposite
Side of Board
Henry W. Ott
HOC
ELECTROMAGNETIC
COMPATIBILITY
MEA - 01223
1998
Ground Plane Voltage Measurements
(Peak to Peak Voltage)
Ground Plane
I
Via
6
1
88 mV 15 mV
15 mV
15 mV
1 1 1
Henry W. Ott
HOC
ELECTROMAGNETIC
COMPATIBILITY
0 1
0.1
1.0
10
100
2 3 4
3.5 2.5 1.5 0.5
GROUND PLANE INDUCTANCE NEAR VIA
1996
nH/inch
Inches from Via
MEA - 00218
Henry W. Ott
HOC
ELECTROMAGNETIC
COMPATIBILITY
DECOUPLING NETWORK - EQUIVALENT CIRCUIT
DIG 00263
PWB
Trace
Inductance
Decoupling
Capacitor
Integrated
Circuit
15 H
5 H
5 H 3 H
R
C
2 H
1998
Henry W. Ott
HOC
ELECTROMAGNETIC
COMPATIBILITY
MULTIPLE CAPACITORS
DEC - 01017A
1997
1
2
1
1
1
2
2
2
L/2
L/2
C
C
C
Ct = C
Lt = L
L/2
L/2
L/2
L/2
L/2
L/2
C C
L/2
L/2
L/2
L/2
L/2
L/2
C
C
C
Ct = 2C
Lt = L
Ct = 2C
Lt = L/2
Lt = L/3
Ct = 3C
General Equation
Ct = NC
Lt = L/N
For N Capacitors
of Value C, Each
in Series With an
Inductance L
Henry W. Ott
HOC
ELECTROMAGNETIC
COMPATIBILITY
DECOUPLING
! It is Difficult to Achieve Good Decoupling at High Frequencies
(> 50 MHz)
! One Way to Achieve This is With Multiple Capacitors (2-50)
Make Them The Same Value
Spread Them Out Physically
! Another Approach is by Using Embedded PCB Capacitance
! Interdigitated Power & Ground Pins Helps Lower the IC Lead
Inductance
! One of the Biggest Limitations in Using Decoupling Capacitors
is the Inductance of the Pad to Via Trace.
Use Multiple Vias, or
Pad in Via Technology to Reduce This
! Another Approach is to use Multiple Capacitors Inside the IC
Package Itself
! Isolated Power Planes Can be Helpful in Minimizing the Bad
Side Effect of Poor Decoupling But Does Not Solve the Basic
Problem
SI - 01017
2000
Henry W. Ott
HOC
ELECTROMAGNETIC
COMPATIBILITY
SIGNAL INTEGRITY (SI) & EMC
! Signal Integrity: How a Signal
Effects Itself
! Signal Integrity: Usually
Concerned With Millivolts &
Milliamps
! EMC: How a Signal Effects
Others
! EMC: Usually Concerned With
Microvolts & Microamps
SI - 01005
2000
Henry W. Ott
HOC
ELECTROMAGNETIC
COMPATIBILITY
EMC & SIGNAL INTEGRITY
SI - 01006
2000
Physical PCB
Layout
Electrical
Design
EMC & Signal Integrity
Henry W. Ott
HOC
ELECTROMAGNETIC
COMPATIBILITY
ELECTRICAL & PHYSICAL PARAMETERS
! Physical PCB Layout
Copper
Dielectric
Traces
Vias
Pads
! This is What We Build
! Electrical Parameters
Inductance
Capacitance
Resistance
Characteristic Impedance
! This is What The Signal Sees
SI - 01015
2000
Henry W. Ott
HOC
ELECTROMAGNETIC
COMPATIBILITY
THERE ARE FOUR SOURCES OF
SIGNAL DISTORTION
! The Signal Net Itself
Discontinuities
Reflections
Attenuation
! Crosstalk
! Power & Ground Noise
Ground Bounce
Decoupling
! External Noise Sources
Radiated
Conducted
SI - 01011
2000
Henry W. Ott
HOC
ELECTROMAGNETIC
COMPATIBILITY
HIGH DENSITY INTERCONNECT
! Chip Scale Packaging (CSP)
Ball Grid Arrays
Chip on Board
Flip Chip
Reduced Pkg. Inductance
! System on a Chip (SOC)
Large I/O Counts (>500)
! PCB Layout/Stackup
Closer Spaced Layers
Elimination of Surface Layer
Traces
Transmission Lines
Faraday Shields
! Testability Issues
Test Point Access
! PCB Materials
FR-4
Polyamide
Ceramic/Glass
PolyTetraFluroEthelyne (PTFE)
! Vias
Microvias (<6 mil)
Via in Pad
Blind Vias
Buried Vias
! Drilling Techniques
Laser
Plasma
Photo-Defined
ADIG - 01003A
2000
Denser, Faster, Smaller Denser, Faster, Smaller Denser, Faster, Smaller Denser, Faster, Smaller
Henry W. Ott
HOC
ELECTROMAGNETIC
COMPATIBILITY
IC PACKAGE INDUCTANCE
IC - 01066
1998
200 400 600 800 1000 1200 0
Package Pin Count
5
10
15
20
0
I
n
d
u
c
t
a
n
c
e

(
n
H
)
Flip Chip
B
G
A
P
Q
F
P
Ref: Lau, p. 37
Henry W. Ott
HOC
ELECTROMAGNETIC
COMPATIBILITY
TRANSMISSION LINE LOSSES
! Skin Effect
! Dielectric Loss
! Ground Plane Loss
! Surface Roughness
! Radiation Losses
ADIG - 01001
2000
Henry W. Ott
HOC
ELECTROMAGNETIC
COMPATIBILITY
SUMMARY
(TRANSMISSION LINE LOSSES)
! For Traces Shorter Than 12 You Can Usually
Ignore all Losses up to 1 GHz.
! Above 1 GHz Skin Effect Losses Become
Significant
! Above 3 GHz Dielectric Losses Become
Predominant
ADIG - 01024
2000
Henry W. Ott
HOC
ELECTROMAGNETIC
COMPATIBILITY
IN SUMMARY
! The Difference Between Signal Integrity (SI) & EMC
is Why You Do Something, Not What You Do
For EMC You Do Something to Minimize the
Emissions and Susceptibility or For Regulatory
Compliance
For Signal Integrity You Do The Same Thing to
Make the Circuit Work Reliably
SI - 01022
2000
Henry W. Ott
HOC
ELECTROMAGNETIC
COMPATIBILITY
NEW TECHNOLOGY
! Evolution of New Technology
State of the Art
Leading Edge
Commodity
! Embedded Capacitance
! Micro-Vias, Buried Vias. Blind Vias
! Chip Scale Packaging
! New PCB Materials
SYS - 01009
2000
Henry W. Ott
HOC
ELECTROMAGNETIC
COMPATIBILITY
BE INNOVATIVE
! Understand the Basic Principles of EMC & SI
and Apply them in New Innovative Ways
! Dont be Afraid to Do Things Differently
! Fund Some R & D With Respect to EMC & SI
! Consider New Technologies
! Whats New Today Will Probably be Common
Tomorrow
! Continue to Learn and Educate Yourself
! Remember, Whatever You Did Last Time Will
Probably Not Work Next Time
SYS - 01010
2000
Henry W. Ott
HOC
ELECTROMAGNETIC
COMPATIBILITY
REFERENCES
! Ott, H. W., Noise Reduction Techniques in Electronic Systems, Second
Edition, Wiley Interscience, 1988.
! Johnson, H. W. & Graham, M., High-Speed Digital Design, Prentice-Hall,
1993.
! Montrose, M. I., Printed Circuit Board Design Techniques for EMC
Compliance, IEEE Press, 1996.
! Fitts, M., The Truth About Microvias, Printed Circuit Design, February
2000.
! Edwards, T. C., Foundations of Microstrip Circuit Design, Second
Edition, John Wiley & Sons, 1992.
! IPC-D-317A, Design Guidelines for Electronic Packaging Utilizing High
Speed Techniques, 1995.
! Wadell, B. C., Transmission Line Design Handbook, Artech House, 1991.
! Johnson, H., Why Digital Engineers Dont Believe in EMC, IEEE EMC
Society Newsletter, Spring, 1998.
! Lau, J. H., Ball Grid Array Technology, McGraw-Hill, 1995.
! IEEE EMC Society web page at <www.emcs.org>.
! Henry Ott Consultants web page at <www.hottconsultants.com>.
2000
REFERENCES