03 PCIe 3.0 PHY Electrical Layer Requirements Final

PCI Express® 3.
0 PHY Electrical
Layer Requirements
Dan Froelich
Intel Corporation
* Third party marks and brands are the property of their respective owners.
Agenda
PHY Requirements
Preliminary Jitter Budget
Statistical Simulation Tools
3.0 PHY Rate
Transmitter Specification
9 PLL Bandwidth
9 Reference Location
9 Timing Parameters
9 Equalization
Reference Clock Specification
Receiver Specification
Major Form Factor Work Areas
Next Steps
PCI-SIG Confidential Copyright © 2008, PCI-SIG, All Rights Reserved 2

PCIe® 3.0 Electrical Requirements
Backwards Compatibility
9 Gen1/Gen2 cards must operate in Gen3 slots at Gen1/Gen2 performance
9 2.0 clocking architectures must be supported.
Compatible with 2.0 Power Budgets
9 Low PHY Power Consumption
Cost: No required changes to connectors, clocks, materials, HVM
manufacturing practices.
9 Extreme server channels may require channel optimizations.
BER of E-12 or better.
At least 2x effective data rate of PCIe 2.0 (5.0 GT/s)
Channel Length Support
9 Client
– 1 Connecter, 14” end to end, microstrip, FR4.
9 Server
– 2 Connector, 20” end to end, stripline, FR4.

System Jitter Budget 8.0 GT/s
Jitter Max Dj (ps) Max RJ Max Dj (ps) Max RJ
Contribution 5.0 GT/s (ps RMS) 8.0 GT/s (ps RMS)
5.0 GT/s 8.0 GT/s
TX 30 1.4 7 1.6
Ref Clock 0 3.1 0 1.0
Channel 58 0 N/A* N/A*
RX 60 1.4 11.8 3.6
*Simluation with Statistical Tool Required To Capture Channel Interactions

PCI-SIG Confidential
Similar PercentagesCopyright
Assumed © 2008, PCI-SIG, All Rights Reserved
at 10 GT/s For Rate Investigation 4
Rate Selection Process
Select worst case channels.
9 Several companies provided channel models for HVM
2.0 client and server systems at length target limits.
Use statistical simulation tools
Analyze rates that can provide ~ 2x data
throughput increase
9 8 GT/s with scrambling.
9 10 GT/s with 8b/10b.
Analyze different receiver equalization methods
9 CTLE
9 DFE

Statistical Simulation Tools
Provides jitter relief by moving jitter from Dj bin to Rj bin
9 For a given channel, enables I/O designers to determine what type, order and
equalization resolution is required for a BER target
9 Accurately models high frequency Tx jitter
Uses statistically weighted data patterns

9 More accurate, less conservative than PDA
Operates on pulse response of channel

9 Comprehends x-talk, ISI, reflections, etc.
Accurately models both Common Refclk and Data Driven architectures

9 Accurately models the interaction of CDRs and ISI
9 Simulates clock models with supply noise sensitivity, device thermal noise,
duty-cycle error and jitter amplification

E.g.: Statistical Treatment of
Jitter
Consider TMIN_PULSE parameter
9 Defined to limit channel induced jitter amplification
5.0G spec defines TMIN_PULSE as 0.1 UI (max)

9 5.0G spec makes no assumptions regarding Dj/Rj breakdown
9 This method of budgeting TMIN_PULSE assumes jitter is 100% bimodal Dj
9 Equivalent to 20 ps Dj, 0 ps Rj
Analysis of Tx jitter sources yields different results

9 Jitter over 1.5G – Nyquist will generate jitter amplification
9 Rj and Dj over this range tend to be spectrally flat
9 Substantial reduction of Dj can be achieved

Statistical Signaling Analysis
Tx Clock Rx Sampling Clock
Tx Lossy Rx
Channel impulse
response
Statistical ISI
Analysis
High-frequency,
uncorrelated Tx Pre-aperture Post-aperture
jitter distribution BER eye BER eye
Equalization
coefficients Xtalk impulse
Rx sample timing &
responses
voltage uncertainty
Modulation distributions

Client Channel Configuration
Seg Description
A MCH PKG
B Break Out
C MB Main 7”
D MB post cap
H
F Add in card main 3”
G Add in card PKG Break out G
H Add in card PKG
F
Figure Key C
A B
- Via
- Microstrip
- Stripline D

HVM Server Channel
Configuration
Two Connectors
Mostly Stripline Routing
20” Total Trace Length CEM
9 4” AIC connector Receiver package
9 4” Riser .050” .010”

.050” .010”
4”
Riser
9 16” Main Board Board
4” Add in Card
Transmitter 0201 (0402 widely used)
package
.020”
.020” 0.5” 11” .020”
.020”
.050”
.050” .050”
.050”
Mother board
Client Channel - Frequency
and Pulse Responses
The insertion loss at 10GT/s is 6dB more than at
8GT/s
9 IL at 4GHz is -13.5dB (8GT/s)
0.45
0
IL 8GT/s
0.4
-10 Aggres1 10GT/s
Aggres2
0.35
-20
0.3
-30
0.25
dB
-40
V
0.2
-50 0.15
-60 0.1
-70 0.05
-80 0
-90 -0.05
0 2 4 6 8 10 -4 -2 0 2 4 6 8 10 12 14 16 18 20
9
Freq x 10 UI
Sample BER Eye Diagrams
TX = [0.9 -0.1]
TX = [0.69 -0.31] DFE =[0.1563 0.0781 0.0352 0 0.0156 0.0117]
0.4
0.4 EQ pulse response
EQ pulse response Un-EQ pulse
Amplitude (V)
Amplitude (V)
Un-EQ pulse response 0.3 response

0.3
8GT/s 0.2 10GT/s

0.2
0.1 1.0 UI
0.1 1.0 UI
0
0
4 5 6 7 8 4 5 6
Time (nsec) Time (nsec)
0 0.15 0
0.15
EH = 27mV
EH = 16mV
0.1 EW = 11ps -2
0.1 EW = 10ps -2
-0.05 -4 -0.05 -4
Voltage
Voltage
0 -6 0 -6
-0.05 -8 -0.05 -8
-0.1 different equalization

-10 settings
-0.1 -10
TX = [1]
TX = [1] DFE =[1:6]
-0.15 -12 -0.15 -12
20 40 60 80 100 120 ps 20 40 60 80 100 ps

HVM Server Channel - Frequency
and Pulse Responses
0 0.45
IL
0.4 8GT/s
-10 Aggres1
10GT/s
Aggres2
0.35
-20
0.3
-30
0.25
dB
-40
V
0.2
-50
0.15
-60
0.1
-70 0.05
-80 0
-90 -0.05
0 2 4 6 8 10 -4 -2 0 2 4 6 8 10 12 14 16 18 20
Freq 9
x 10 UI

Simulation Results (Nominal)
Equalization Sweep Equalization Sweep
0.08 0.04 Pass
8GT/s 0.02 8GT/s
0.06 14” Client Channel
Eye Height (V)
Eye Height (V)

0.04 -0.02
Fail
10GT/s Pass -0.04
0.02
-0.06 10GT/s
0 -0.08 20” Server Channel
-0.1
-0.02 Fail
Power & Area -0.12 Power & Area
-0.04 -0.14
TX EQ [1] [1] [1] [1] [1] [1] TX EQ [1] [1] [1] [1] [1] [1]
CTLE 1st 1st 1st CTLE 1st 1st 1st
DFE DFE [2 3] [1 2] [1-4 ] [1-6 ]
[2 3] [1 2] [1-4 ] [1-6 ]
0.25
8GT/s
0.2
7” Client Channel
Eye Height (V)
0.15
0.1
10GT/s
0.05
Pass
-0.05
Power & Area Fail
-0.1
TX EQ [1] [1] [1] [1] [1] [1]
CTLE 1st 1st 1st
DFE [2 3] [1 2] [1-4 ] [1-6 ]
Simulation Results (Est W/C)
Equalization Sweep Equalization Sweep
0.08 0.04 Pass
8GT/s 0.02
0.06 14” Client Channel Fail
Eye Height (V)
Eye Height (V)

0.04
Pass -0.02 8GT/s
-0.04
0.02
-0.06 10GT/s
0 Fail -0.08 20” Server Channel
10GT/s
-0.1
-0.02
Power & Area -0.12 Power & Area
-0.04 -0.14
[1] [1] [1] [1] [1] [1] TX EQ [1] [1] [1] [1] [1] [1]
TX EQ
CTLE 1st 1st 1st CTLE 1st 1st 1st
DFE DFE [2 3] [1 2] [1-4 ] [1-6 ]
[2 3] [1 2] [1-4 ] [1-6 ]
0.25
8GT/s
0.2
7” Client Channel
Eye Height (V)
0.15
0.1
10GT/s Pass
0.05
0 Fail
-0.05 Power & Area
-0.1
TX EQ [1] [1] [1] [1] [1] [1]
CTLE 1st 1st 1st
DFE [2 3] [1 2] [1-4 ] [1-6 ]
Rate Selection Summary
8GT/s is feasible over channels of interest with
reasonable equalization
10GT/s imposes a power penalty

9 8G-10G power increase somewhere between linear and quadratic
10GT/s imposes a cost penalty

9 Lower loss PCB materials
9 Backdrilled vias
9 Layout restrictions
-------------------------------------------------------------------------------

PCIe 3.0 Tx Spec Subsection
Transmitter Electrical parameters
9 Transmit PLL Characteristics
9 Tx Specification Location
9 Tx Timing Specifications
9 Adaptive TX Equalization?

Transmit PLL Characteristics
8.0 GT/s requires Tx PLL bandwidth and jitter peaking to be
more tightly controlled than for 5.0 GT/s
2.0 Mhz 3dB Peaking

9 SSC limits low end
4.0 Mhz 3dB Peaking
5.0 Mhz 1dB Peaking
8.0 Mhz 3dB Peaking
16 Mhz 3dB Peaking

Base Spec TX Spec Location
TX specification at silicon pins (2.0 base location)
9 Too difficult to quantify package interaction with unknown channel
TX specification at die pad
9 Current spec direction
9 All relevant parameters can be specified at point that is independent of
package and channel
9 Direct measurements not possible
– Standard de-embedding algorithm/methodology needed in base spec.
TX specification at the end of reference channel(s)
9 Other option discussed in EWG
9 TX is compliant if it can produce passing signaling through a worst case
channel(s)
9 Can a small number of reference channels capture all worst case
Tx/package/channel interactions?
9 Contributions from various TX variables not clearly separated
Transmitter specs
Parameter Description 5.0 GT/s 8.0 GT/s
UI unit interval 200 ps ±300 ppm 125 ps ±300 ppm
VTX-DIFF-PP Differential p-p Voltage Swing .8 – 1.2 V (pins) .1 – 1.2 V (die)
VTX-RESOLUTION Minimum Resolution For Voltage N/A 50 mV
Adjustments
TTX-1UI-RJ-8G Rj over 1UI Width N/A .48 ps RMS max

TTX-2UI-RJ-8G Rj over 2UI Width N/A TBD
TTX-UI-DJ-8G Per UI Deterministic Jitter (1.5 Ghz +) N/A 4 ps max
TTX-HF-RJ-8G TX Random Jitter (10 Mhz – 1.5 Ghz) 1.4 ps RMS max 1.6 ps RMS max
TTX-HF-DJ-DD-8G HF TX Deterministic Jitter 30 ps max 7 ps max
TTX-LF-RMS-8G LF TX Jitter (10 Khz – 10 Mhz) 3.0 ps RMS max TBD
Substantial differences between 5.0 and 8.0 GT/s based on need to account for additional
jitter effects (jitter amplification, etc)

Transmitter specs continued
Parameter Description 5.0 GT/s 8.0 GT/s
PKGTX-DIE-CAP Equivalent Package Die Capacitance N/A 1 pf Max
PKGTX-PIN-CAP Equivalent Package Pin Capacitance N/A .5 pf Max
PKGTX-LEN Equivalent Package Length N/A 50 – 1500 mils
ZTX-DIFF-DC DC differential TX Impedance N/A 120 ohm max

LTX-SKEW Lane-to-Lane Output Skew 500 ps + 4UI max TBD
CTX AC Coupling Capacitance 75 – 200 nf 180 – 200 nf
TX Equalization
9 2 or 3 tap
9 Adjustable coefficients may be required
– Complicates TX silicon and form factor testing

Refclk Spec Subsection
Reference Clock Electrical parameters
9 Refclk Architectures
9 Post processing steps
9 Jitter definitions

Clock Architectures
PCIe Base spec defines two distinct Refclk architectures at 5.0
GT/s and 8.0 GT/s: common clock and data clocked
9 At 2.5 GT/s spec does not differentiate between 2 cases, but implicitly
supports both
Jitter margins for the two differ at 5.0 GT/s -- same at 8.0 GT/s.
9 PLL and CDR bandwidth changes remove any difference in jitter values
between two architectures
Tx Rx Tx Rx
channel channel
latch latch latch CDR
CDR Tx
PLL
Tx Rx
channel Refclk PLL Refclk
PLL
Common Clock Architecture Data Clocked Architecture

Refclk Post Processing for 8.0 GT/s
Post processing removes jitter components that are
measurement artifacts or otherwise irrelevant
This process is NOT clock architecture dependent
Common Clocked and Data Clock
< 10 MHz jitter components No SSC removal
PLL difference function (or min PLL)
0.01- 10 MHz step BPF
> 10 MHz jitter components PLL difference function (or max PLL)
10 MHz step HPF
Edge filtering
PLL diff function: Difference between min and max PLL bandwidths
Edge filtering: Smoothing function to reduce effects of sampling aperture inaccuracy
Step filter Separates jitter into <10 MHz and ≥10 MHz bins

Reference Clock Data
Obtained Connector Reference Clock Data With Several PCI
Express 2.0 Systems
9 Measured with PCI-SIG® CLB 2.0 test fixture and RT scope.
Analyzed HF Jitter with PCIe 2.0 and 3.0 Filters
9 2.0 (3.1 ps RMS limit)
– H1 16 Mhz, 3db Peaking, 40 db/dec rolloff
– H3 1.5 Mhz High Pass Step.
9 3.0 (1.0 ps RMS limit)
– H3 10 Mhz Step

System A
PCIe 2.0 filter
9 2.22 ps RMS
PCIe 3.0 filter

9 .24 ps RMS
9 Existing compliant PCIe
2.0 systems can meet 3.0
HF jitter limits
System B
PCIe 2.0 filter
9 4.21 ps RMS
PCIe 3.0 filter

9 .45 ps RMS
9 PCIe 2.0 HF limits are
often more restrictive
than 3.0 limits
System C
PCIe 2.0 filter
9 7.25 ps RMS
PCIe 3.0 filter

9 1.25 ps RMS

PCIe 3.0 Channel Spec – Major
Changes
Tx package defined in terms of CDIE, CPAD, and a swept length
Rx package defined in terms of CDIE, CPAD, and a swept length
Tx jitter is defined in terms of Dj and an Rj distribution
Statistical simulation tools used to capture TX, channel, RX

interactions
A reference Rx equalization algorithm is applied to raw data as

it appears at the Rx die pad
PCIe 3.0 Rx Spec Subsection
PCIe 3.0 Receiver Specification
9 Major Change Summary
9 Scrambling Impact
9 RX Measurement Methodology

Major RX Specification Changes
Jitter and voltage limits referenced to die pad
Rx PLL bandwidth reduced to 2-4 Mhz.
RX CDR bandwidth increased to 10 Mhz minimum.
Jitter defined with bandlimited TJ and Dj components
RX return loss replaced with CDIE, CPIN, CLENGTH
Jitter measured after applying inverse equalization
algorithm

Base Spec Rx Equalization
RX equalization is required.
A specific RX equalization algorithm/method is not required by
the specification.
It is expected that most designs will be able to pass receiver
base spec requirements with a simple technique like single
pole CTLE.
Impact on RX Measurement Methodology (Tolerance Test)
9 Apply baseline receiver equalization algorithm to calibrate test source
OR
9 Calibrate noise sources with open eye and assume linearity as sources
are increased
Impact on form factor specifications
9 May have to apply baseline receiver equalization algorithm as part of
TX data post processing.
Impact of Scrambling
PHY Impact
9 Statistical DC balance only: DC wander
9 Statistical transition density: CDR tracking
9 Both appear to be solvable with minor circuit changes
Ongoing PHY Work

9 Determine magnitude of DC wander and potential need for
mitigation in Tx or Rx
9 Quantify frequency wander for DD architecture in presence of
SSC and no data edges

What is Baseline Wander?
• In an AC coupled data transmission system, low
freq signal components are removed by the HPF
• The average or DC value of the signal becomes

data pattern dependent
• This causes a ‘wandering’ average
• The severity of baseline wander is dependent on

the cut-off freq of the HPF and the PSD of the
signal below this cut-off
C Rcvr
Data
Rsrc
src

Simple Channel Model: With On-Die Capacitance
3 different HPF bandwidths
Case 1: A nominal capacitance 1pF with 100kW resistor for low cutoff
Case 2: A stretch (500kW) resistor case
Case 3: Similar to Case 1 with a 200nF AC line cap
Sim conditions: 1.0 Vpp @ Tx, 106 random bits

R2-C1 BW R3-C2 BW BLW p-p
Case # R1 (Ω) C1 (nF) R2 (Ω) C2 (pF) R3 (KΩ) (KHz) (KHz) (mV)
1 50 75 50 1 100 42.4 1591.6 112.5
2 50 75 50 2 500 42.4 159.2 33.5
3 60 200 60 1 100 13.3 1591.6 95
C1 C2
V s rc V in R1: source resistance
Vout
C1: off-chip capacitor
R1
R2 R3
R2: termination resistance
V cm C2: on-die capacitance
R3: on-die resistance
On Die RC Dominates Wander If On Die Capacitance Present

Baseline wander vs. On-Die HPF bandwidth
Sweep on-chip RC keeping off-chip RC constant (R1=50Ω, R2=50 Ω, C1=75nF)
As on-die HPF cut-off freq approaches off-chip bandwidth (=42.4 KHz), baseline
wander reduction saturates as expected
BLW
R3 C2 R3-C2 BW sigma BLW p-p
(Kohm) (pF) (KHz) (mV) (mV)
1000 5 31.8 3.3 20
500 5 63.7 3.9 24.4
500 2 159.2 5 33.8
500 1 318.4 6.3 45
250 1 636.7 8.5 64.3
100 1 1591.8 13 106.1
50 1 3183.5 18.1 159.1
50 0.5 6367.1 25.3 243.1
10 1 15917.7 39.6 390.4
5 1 31835.4 55.8 504.7
5 0.5 63670.8 78.9 687.5
C1 C2
V s rc V in Vout
R1
R2 R3
V cm
On Die RC Dominates Wander If On Die Capacitance Present

Effect of Transmit Equalization
BLW scales linearly with transmit amplitude, i.e. it is a BLW vs. Tx amplitude
function of pre-aperture eye height

Tx equalization attenuates low freq components resulting
in reduced BLW
Tx EQ sims:
¾ 1 tap (postcursor) de-emphasis Tx Eq
¾ Sweep tap coefficient for same Tx amplitude (1Vp-
p)
¾ BLW with and without on-chip cap are simulated
(nominal case: R1=50 Ω, C1=75nF, R2=50Ω,
C2=1pF, R3=100 Ω)
BLW p-p
BLW p-p w/o on-
EQ w/ on-chip Pre-aperture chip cap
setting cap (mV) eye height (V) (mV)
0 110 1.0 10.6
0.1 88 0.8 8.5
BLW vs. EQ setting
0.2 66 0.6 6.4
0.25 55 0.5 5.3
0.3 44 0.4 4.2
0.4 22 0.2 2.1

Base Line Wander Next Steps
Ongoing simulation work to determine accurate
worst case number.
Analyze possible mitigation techniques
9 Bit Stuffing
9 DC restoration circuit in RX
9 DC coupled receiver
9 Combinations of above approaches
9 Other techniques?

Form Factor TX
Measurement Methodology
Option 1 - Specify standard fixture(s) requirements and include in determining form
factor limits (CEM 2.0 methodology)
9 Pros
– Don’t need to specify de-embedding algorithm/procedure that can be applied consistently across
industry
– PCI-SIG can provide standard fixtures to members
9 Cons
– Will require tight control of fixture parameters and likely add cost to fixtures
• Fixtures may be high cost anyway if they have to provide receiver feedback to drive TX adaptive EQ to
different states
• Fixture cost still small relative to test equipment cost
– May not be possible at 8 GT/s. (investigation needed)
Option 2 – Specifying standard de-embedding process/requirements for any form

factor fixture (don’t include fixture in form factor limits)
9 Pros
– A variety of fixtures with different characteristics could provide equivalent results
9 Cons
– Need to specify de-embedding algorithm/procedure that can be applied consistently across
industry
– Getting accurate simulation results exactly at the edge finger/connector may be difficult

Form Factor Reference Clock Testing
Option 1 – Test Reference Clock Separately
9 Pros
– Simpler measurement setup than dual port
9 Cons
– Removes ability to trade off clock and data jitter at system level
– Must account for not having a clean reference clock for standard motherboard TX test
Option 2 – Use Dual Port Simultaneously Clock/Data (Methodology Specified in

CEM 2.0)
9 Pros
– Allows tradeoff of data and clock jitter at system level
– Don’t have to worry about how to test real motherboard without clean clock
– No issues testing with SSC on
9 Cons
– More complex measurement setup – but already proven for CEM 2.0
– Ability to trade off clock and data jitter adds little relief with clock jitter budget at 1 ps Rj (RSS
with other other parts of RJ budget)

Form Factor Methodology For 3.0
Need to investigate whether CEM 2.0 methodology
for determining connector voltage/jitter limits will
work for 3.0
9 Less margin available
Additional constraints beyond jitter/voltage margin
may be needed to preserve enough solution space
for 3.0
9 TDR
9 Return Loss
9 Other . . .

Major Work Items Upcoming
Demonstrate method of de-embedding to die pad
9 Good progress: several options being evaluated
Close on Tx equalization choices

9 Trainable vs. fixed coefficients
Resolve DC wander effects

9 Rx voltage margin, effective CDR BW impact
Long server channel mitigation costs/effectiveness

Future Plans
Rev0.3 Rev0.5
9 Data rate, encoding set 9 Tx, Rx reference planes
9 Tx, Rx parameter tables defined
9 All parameters defined
9 Being reviewed by EWG now
9 Tx, Rx equalization defined
Rev0.7 Rev0.9
9 All parameter values stable 9 Minor formatting/typo edits
9 Statistical scripts included in
spec

Backup
CEM 2.0 Methodology Review

System Board TX Eye Methodology
Simulate end to end eye diagrams
Identify all end to end failures (worst case pattern)

– 120 mVolt Eye Height (Base Spec Rx Pin Limit)
– 142 ps Eye Width (Interconnect only) (Base Spec Channel Limit)
142 ps 120 mV
50 ps
Worst Case Patterns
Peak Distortion Analysis
9 Deterministically Calculates Worst Case Patterns Given
– Channel S Parameters
– Pulse Response
9 Used For Simulation Data In This Presentation
Differences From Pseudo Random or CMM Patterns Can Be Very Large
(~ 30 ps eye width)

System Board TX Eye Methodology
Simulate end to connector eye diagrams

Ideal Fixture
2” 85 Ohm
Use CMM pattern as with real world test

Correlate with end to end worst case pattern
failures
CEM eye specifications include ideal fixture

9 No need to de-embed if similar fixture used

Simulation Methodology
The resultant eyes of the End
to End and CEM simulations
are plotted against each other
for a large number of cases
A Horizontal line is drawn CEM
with respect to the End to End failures
eye to signify insufficient
opening in the system
A Vertical line is drawn such
that no End to end failures
are to the right
Instances in the lower right End to end
quadrant would indicate End failures
to End failures not screened
out by CEM
Instances in the upper left
quadrant are cases which
work End to End, but are
screened out by the CEM*

03 PCIe 3.0 PHY Electrical Layer Requirements Final

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PCI Express® 3.

PCI-SIG Confidential Copyright © 2008, PCI-SIG, All Rights Reserved 2

PCI-SIG Confidential Copyright © 2008, PCI-SIG, All Rights Reserved 3

Ref Clock 0 3.1 0 1.0

Channel 58 0 N/A* N/A*

RX 60 1.4 11.8 3.6

*Simluation with Statistical Tool Required To Capture Channel Interactions

PCI-SIG Confidential Copyright © 2008, PCI-SIG, All Rights Reserved 5

 Uses statistically weighted data patterns

 Operates on pulse response of channel

 Accurately models both Common Refclk and Data Driven architectures

PCI-SIG Confidential Copyright © 2008, PCI-SIG, All Rights Reserved 6

 5.0G spec defines TMIN_PULSE as 0.1 UI (max)

 Analysis of Tx jitter sources yields different results

PCI-SIG Confidential Copyright © 2008, PCI-SIG, All Rights Reserved 7

PCI-SIG Confidential Copyright © 2008, PCI-SIG, All Rights Reserved 8

PCI-SIG Confidential Copyright © 2008, PCI-SIG, All Rights Reserved 9

9 4” Riser .050” .010”

Un-EQ pulse response 0.3 response

8GT/s 0.2 10GT/s

-0.1 different equalization

PCI-SIG Confidential Copyright © 2008, PCI-SIG, All Rights Reserved 12

PCI-SIG Confidential Copyright © 2008, PCI-SIG, All Rights Reserved 13

Eye Height (V)

Eye Height (V)

 10GT/s imposes a power penalty

 10GT/s imposes a cost penalty

PCI-SIG Confidential Copyright © 2008, PCI-SIG, All Rights Reserved 16

9 Transmit PLL Characteristics

PCI-SIG Confidential Copyright © 2008, PCI-SIG, All Rights Reserved 17

 2.0 Mhz 3dB Peaking

 4.0 Mhz 3dB Peaking

 5.0 Mhz 1dB Peaking

 8.0 Mhz 3dB Peaking

 16 Mhz 3dB Peaking

TTX-1UI-RJ-8G Rj over 1UI Width N/A .48 ps RMS max

PCI-SIG Confidential Copyright © 2008, PCI-SIG, All Rights Reserved 20

ZTX-DIFF-DC DC differential TX Impedance N/A 120 ohm max

PCI-SIG Confidential Copyright © 2008, PCI-SIG, All Rights Reserved 21

9 Post processing steps

PCI-SIG Confidential Copyright © 2008, PCI-SIG, All Rights Reserved 22

Common Clock Architecture Data Clocked Architecture

 Edge filtering: Smoothing function to reduce effects of sampling aperture inaccuracy

PCI-SIG Confidential Copyright © 2008, PCI-SIG, All Rights Reserved 24

PCI-SIG Confidential Copyright © 2008, PCI-SIG, All Rights Reserved 25

 PCIe 3.0 filter

 PCIe 3.0 filter

 PCIe 3.0 filter

PCI-SIG Confidential Copyright © 2008, PCI-SIG, All Rights Reserved 28

 Tx package defined in terms of CDIE, CPAD, and a swept length

 Rx package defined in terms of CDIE, CPAD, and a swept length

 Tx jitter is defined in terms of Dj and an Rj distribution

 Statistical simulation tools used to capture TX, channel, RX

 A reference Rx equalization algorithm is applied to raw data as

PCI-SIG Confidential Copyright © 2008, PCI-SIG, All Rights Reserved 30

PCI-SIG Confidential Copyright © 2008, PCI-SIG, All Rights Reserved 31

 Ongoing PHY Work

PCI-SIG Confidential Copyright © 2008, PCI-SIG, All Rights Reserved 33

• The average or DC value of the signal becomes

• This causes a ‘wandering’ average

• The severity of baseline wander is dependent on

PCI-SIG Confidential Copyright © 2008, PCI-SIG, All Rights Reserved 34

 Sim conditions: 1.0 Vpp @ Tx, 106 random bits

Uses statistically weighted data patterns

Operates on pulse response of channel

Accurately models both Common Refclk and Data Driven architectures

5.0G spec defines TMIN_PULSE as 0.1 UI (max)

Analysis of Tx jitter sources yields different results

10GT/s imposes a power penalty

10GT/s imposes a cost penalty

2.0 Mhz 3dB Peaking

4.0 Mhz 3dB Peaking

5.0 Mhz 1dB Peaking

8.0 Mhz 3dB Peaking

16 Mhz 3dB Peaking

Edge filtering: Smoothing function to reduce effects of sampling aperture inaccuracy

PCIe 3.0 filter

PCIe 3.0 filter

PCIe 3.0 filter

Tx package defined in terms of CDIE, CPAD, and a swept length

Rx package defined in terms of CDIE, CPAD, and a swept length

Tx jitter is defined in terms of Dj and an Rj distribution

Statistical simulation tools used to capture TX, channel, RX

A reference Rx equalization algorithm is applied to raw data as

Ongoing PHY Work

Sim conditions: 1.0 Vpp @ Tx, 106 random bits

Option 2 – Specifying standard de-embedding process/requirements for any form

Option 2 – Use Dual Port Simultaneously Clock/Data (Methodology Specified in

Close on Tx equalization choices

Resolve DC wander effects

Long server channel mitigation costs/effectiveness

Identify all end to end failures (worst case pattern)

Simulate end to connector eye diagrams

Use CMM pattern as with real world test

CEM eye specifications include ideal fixture