Ams Lec 01 Introduction v01

‫ن ا ْلعِْلِم إِاَّل قَلِ ًيل‬ِ ‫وما أُوتِيتم‬
‫م‬
5 August 2021 1442 ‫ ذو الحجة‬26
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Analog/Mixed-Signal Simulation and Modeling
Module 01
Introduction to the ICs and EDA Worlds
Dr. Hesham A. Omran

Integrated Circuits Laboratory (ICL)
Electronics and Communications Eng. Dept.
Faculty of Engineering
Ain Shams University
Module 01: Introduction to the ICs and EDA Worlds
1. Electronics Evolution and the ITRS/IRDS
2. Moore’s Law
3. Modern Moore Concepts
4. Why Don’t We Fabricate ICs in Egypt?
5. The Semiconductors Market
6. Course Information
7. Analog vs Digital Electronics
8. Introduction to Integrated Circuits (ICs)
9. How to Design a Billion Transistor Chip?
10. Introduction to Electronic Design Automation (EDA)
11. Analog IC Design Flow
01: Introduction 2
2. Moore’s Law
01: Introduction 3
Introduction
ENIAC, U.S. Army, 1946 Smart phone

Size → Large hall (> 150m2) Size → Your pocket
Power Consumption ≈ 150kW Power consumption < 1W
01: Introduction 4
Electronics All Around Us
01: Introduction 5
Transistor Evolution
First transistor Trigate Transistor

Contacts separation ≈ 100µm Fin width ≈ 8nm
Bell Labs, 1947 Intel, 2015
01: Introduction 6
Integrated Circuit (IC) Evolution
≈ 13.5mm
≈ 11mm
First IC Quad-core CPU

Only one transistor (+ R + C)! > 109 transistors!
Texas Instruments (TI), 1958 Intel, 2017
01: Introduction 7
Sensing Microsystems
3mm 4mm
ADXL350
Analog Devices, 2012
Complete system on a tiny chip
• 3-axis MEMS* accelerometer
• Interface electronics
• Analog-to-digital conversion
• Memory
First accelerometer • Control logic
B&K, 1940s • Power management
• Digital interface
Simple bulky transducer
Acceleration → Voltage *MEMS = Micro-Electro-Mechanical Systems
01: Introduction 8
A Glimpse of History
❑ 1947: Invention of the transistor
❑ 1957: Soviet Union launched Sputnik (the world's first artificial satellite)
❑ 1958: US government created
▪ NASA: National Aeronautics and Space Administration and
▪ DARPA: Defense Advanced Research Projects Agency
❑ 1958: Invention of the IC
❑ 1960s, 1970s, 1980s: US government heavily funded semiconductor research
▪ VLSI = Very Large Source of Income ☺
❑ 1990: End of cold war, US government funding rapidly decreased
❑ 1991: Academia, government and industry held a workshop to:
▪ Create a common roadmap for semiconductors
▪ Facilitate funding for semiconductor research
01: Introduction [P. Gargini, IRDS, Intel] 9

NTRS / ITRS / IRDS
❑ A roadmap published by a group of (volunteering) semiconductor experts that represent
semiconductor industry associations
❑ NTRS: National Technology Roadmap for Semiconductors
▪ 1992 to 1997: USA
❑ ITRS: International Technology Roadmap for Semiconductors
▪ 1998 to 2016: USA, Europe, Japan, S. Korea, Taiwan
❑ IRDS: International Roadmap for Devices and Systems
▪ 2016-now
❑ Ex: Do the following Google Search

site:https://irds.ieee.org/images/files/pdf/2017/ filetype:pdf
site:https://irds.ieee.org/images/files/pdf/2021/ filetype:pdf
01: Introduction 10
NTRS / ITRS / IRDS
❑ Previously focusing on PPA (power, performance, and area)
❑ Now PPAC = PPA + cost
Yellow: Solutions being pursued Red: No known solutions (yet)
01: Introduction [Tsu‐Jae King Liu, Berkeley, 2012] 11

‫م‬
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Module 01
Dr. Hesham A. Omran

2. Moore’s Law
01: Introduction 13
Moore’s Law
❑ Moore’s law [1965]: Transistor count doubles every year
“The complexity for minimum component costs has

increased at a rate of roughly a factor of two per
year. Certainly over the short term this rate can be
expected to continue, if not to increase. Over the
longer term, the rate of increase is a bit more
uncertain, although there is no reason to believe it
will not remain nearly constant for at least 10 years.“
[Gordon Moore, Electronics Magazine, 1965]
01: Introduction 14
Moore’s Law
❑ Moore’s law [1965]: Transistor count doubles every year
❑ Practically: It doubled every 2-3 years since the 4004 [1970s]
❑ At the end of the day: It is exponential!
01: Introduction [Weste and Harris, 2010] 15

Technology Minimum Feature Size
1
❑ Minimum feature size shrinking 30% (= 0.7 × ≈ ×) every 2-3 years
2
▪ Transistor area (and cost) are reduced by a factor of ?
❑ Device scaling brings new opportunities and challenges!

Technology Node
❑ Historically, the process node name referred to the transistor gate length
▪ Same as M1 half-pitch.
❑ But this is not valid anymore (more about this shortly)
GND VDD
nMOS transistor pMOS transistor

substrate tap well tap
A
GND VDD
Y
p+ n+ n+ p+ p+ n+
n well
p substrate
[Weste and Harris, 2010]
well
01: Introduction substrate tap
tap
[IRDS ES, 2020] 17
01: Introduction 18
The End of Moore’s Law?
01: Introduction 19
‫م‬
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Module 01
Dr. Hesham A. Omran

2. Moore’s Law
01: Introduction 21
Modern “Moore” Concepts
01: Introduction [Wolfgang Arden et. al., ITRS] 22

Modern “Moore” Concepts: MM
❑ More Moore (MM): miniaturization = integration density
▪ Further miniaturization of transistor as per Moore’s law
▪ New materials for performance enhancement (HK, SOI, III-V, etc.)
▪ Addressing lithography limitations (e.g., EUV, double patterning, etc.)
▪ New device architectures
▪ State-of-the-art: FinFET
• Multigate FET proposed in 1988
• Focused research started in 2000
• Commercially available in 2011!
01: Introduction 23
FinFET
❑ Planar CMOS cannot be scaled below 20nm due to excess leakage current and severe short
channel effects.
❑ FinFET: Gate has better control on the channel
▪ Intel’s version is called trigate FET
▪ Generally: Multigate transistor

The Last Step?
Microelectronics Careers 25
Or The Next Step?
Still Too Many Steps! – IRDS 2021
ADT at UCL [https://irds.ieee.org/images/files/pdf/2020/2020IRDS_BC.pdf] 27

Technology Node
❑ Historically, the process node name referred to the
transistor gate length (same as M1 half-pitch).
❑ Most recently, due to various marketing and discrepancies
among foundries, the number itself has lost its exact
meaning.
❑ Gate length has not scaled proportionately with device pitch
(0.7x per generation) in recent generations.
❑ Recent technology nodes (22 nm and below) does not
correspond to any gate length or half pitch!
▪ Just 70% of whatever the name of the node of the
previous generation was!
[https://en.wikichip.org/wiki/technology_node]
01: Introduction [IRDS ES, 2020] 28
IBM 2nm Technology
❑ IBM announcement of 2nm technologies does not correspond to 2nm feature size!
▪ The individual nanosheets are 5nm in height and separated from each other by 5 nm.
01: Introduction [https://www.anandtech.com/show/16656/ibm-creates-first-2nm-chip] 29

IRDS Technology Node Definition

The End of Min Feature Size Scaling

But Still Too Many Steps! – IRDS 2020
ADT at UCL [https://irds.ieee.org/images/files/pdf/2020/2020IRDS_BC.pdf] 32

The different Ages of Scaling
❑ 1975 – 2000: Geometrical scaling
▪ Reduction of horizontal and vertical dimensions
▪ Improved performance of planar transistors
❑ 2000 – 2025: Equivalent scaling
▪ Reduction of only horizontal dimensions
▪ Introduction of new materials and new physical effects
▪ New vertical structures replace the planar transistor
❑ 2025 – 2040: 3D scaling
▪ Transition to complete vertical device structures
▪ Heterogenous integration
❑ Our current bag of innovations can keep CMOS alive till 2040!
01: Introduction [P. Gargini, IRDS, Intel] 33


Modern “Moore” Concepts: MtM
❑ More than Moore (MtM): Diversification
▪ Adding functionalities not associated
with transistor scaling to increase the
value
• Sensors, MEMS, bio, passives, HV,
RF, etc.
▪ 3D integrated circuits
• Through silicon vias (TSVs) connect
the dies together
01: Introduction [https://nhanced-semi.com/technology/about-3d-ics/] 35

Why 3D ICs?
❑ 3D ICs enable heterogenous integration (logic + specialty)
01: Introduction 36
Why 3D ICs?
❑ 3D ICs enable heterogenous integration (logic + specialty)
01: Introduction 37

Modern “Moore” Concepts: BM
❑ Beyond Moore (BM): Beyond CMOS
▪ Find the next switch: many
candidates exist
▪ Quantum computing
▪ Lots of funding by governments
and industry
▪ But no commercial solution
(reliable & cost-effective) available
yet
01: Introduction [IRDS, BC, 2017] 39

‫م‬
َ ُْ ََ
Module 01
Dr. Hesham A. Omran

2. Moore’s Law
01: Introduction 41
How Much it Costs?
❑ TSMC planned 3nm fab is expected to cost $20 Billion.
❑ The Moore’s law train will soon come to a stop.
▪ But not due to physical limits as many have expected!
❑ No chance for Egypt in the semiconductor fabrication business (at least in the near future).
▪ What about other perspectives?

Foundries with a Cutting-Edge Logic Fab
SilTerra
X-FAB
Dongbu
HiTek
ADI ADI
Atmel Atmel
Rohm Rohm
Sanyo Sanyo
Mitsubishi Mitsubishi
ON ON
Hitachi Hitachi
Cypress Cypress Cypress
Sony Sony Sony
Infineon Infineon Infineon
Sharp Sharp Sharp
Freescale Freescale Freescale Pan.
Renesas Renesas Renesas Renesas Renesas
SMIC SMIC SMIC SMIC SMIC STM
Toshiba Toshiba Toshiba Toshiba Toshiba
Fujitsu Fujitsu Fujitsu Fujitsu Fujitsu UMC
TI TI TI TI TI
Panasonic Panasonic Panasonic Panasonic Panasonic
IBM IBM
STM
UMC
STM
UMC
STM
UMC
STM
UMC
STM
UMC
GF GF GF
IBM IBM IBM IBM IBM Sam. Sam. Sam. Sam. Sam. Sam. ?
AMD AMD AMD GF GF
Samsung Samsung Samsung Samsung Samsung TSMC TSMC TSMC TSMC TSMC TSMC ?
TSMC TSMC TSMC TSMC TSMC
Intel Intel Intel Intel Intel Intel Intel Intel Intel Intel ? ?
45/40 32/28 22/20 16/14
180 nm 130 nm 90 nm 65 nm 10 nm 7 nm 5 nm 3 nm
nm nm nm nm
01: Introduction [https://en.wikichip.org/wiki/technology_node] 43
UAE Fab Cancelled
01: Introduction 44
GF Cancelled 7nm Plans
01: Introduction 45
Money is Not the Only Problem!
ADT at UCL 47
India…
01: Introduction 48
The US…
01: Introduction 49
TSMC…
01: Introduction 50
Europe…
ADT at UCL 51
‫م‬
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Module 01
Dr. Hesham A. Omran

2. Moore’s Law
01: Introduction 53
Types of Companies in the VLSI Industry
❑ IDM (integrated device manufacturer): Companies that design and manufacture integrated
circuits (ICs)
▪ Ex: Intel, Samsung, Texas Instruments (TI), etc.
❑ Fabless companies: Companies that focus on IC design only. They don’t have manufacturing
capabilities.
▪ Ex: Qualcomm, Broadcom, Nvidia, etc.
▪ Product companies vs design services companies
❑ Foundry companies (a.k.a. pure-play foundries or merchant foundries): Companies that
focus on IC fabrication only, without having any in-house design capabilities.
▪ Ex: TSMC, Global Foundries, UMC, etc.
❑ EDA companies: Companies that create the software tools used in IC design (EDA tools)
▪ Ex: Synopsys, Cadence, Mentor (now Siemens EDA), etc.
01: Introduction 54
Types of Companies in the VLSI Industry
01: Introduction [SIA Beyond Borders Report, 2016] 55

The Semiconductor Ecosystem

The Evolution of the Semiconductor Ecosystem

Top Semiconductor Companies
Microelectronics Careers [https://www.icinsights.com/news/bulletins/Intel-To-Keep-Its-Number-One-Semiconductor-Supplier-Ranking-In-2020/] 58

More Companies Joining The Field!
More Companies Joining The Field!
Semiconductors Market
❑ Semiconductor sales
revenue worldwide (2019)
▪ ~ 484 billion USD
01: Introduction [https://www.statista.com/statistics/266973/global-semiconductor-sales-since-1988/] 61

Electronics Market
01: Introduction [Source: Synopsys, 2019] 62

Electronics Market
01: Introduction [Source: Cadence, 2017] 63

ICT Market
❑ The 400+ billion semiconductor
industry enables a 4,000+
billion information and
communication technology
(ICT) industry
❑ Egypt’s total revenue (2019)
▪ ~ 57 billion USD
▪ ~ 31 billion (55%) goes for
loans interests
▪ ~ 16 billion (28%) for loans
repayment!
❑ Only 10 billion USD remains
▪ We need 41 billion USD
more in 2019 budget?!
01: Introduction [https://www.statista.com/statistics/268584/worldwide-ict-revenue-since-2005/] 64
The Smartphone Plateau
01: Introduction [https://edition.cnn.com/interactive/2019/09/business/samsung-headquarters-south-korea/index.html] 65

Growing Demand in New Applications
01: Introduction [Synopsys, 2019] 66

Growing Demand in New Applications: Automotive
01: Introduction [Vincent Roche, ADI, ISSCC Plenary Talk, 2018] 67

Growing Demand in New Applications: IoT
01: Introduction [Vincent Roche, ADI, ISSCC Plenary Talk, 2018] 68

IC Industry in Egypt
01: Introduction 69
Why Join The IC Industry?
❑ Highly paid
❑ Challenging job
▪ Makes the most out of your smartness
▪ Not just operation and maintenance
❑ Requires deep technical knowledge
▪ Strongly related to what you learn at university
▪ Keeps you updated with the state-of-the-art
‫م‬
َ ُْ ََ
Module 01
Dr. Hesham A. Omran

2. Moore’s Law
01: Introduction 72
Course Modules
1. Introduction to the ICs and EDA worlds
2. Understand and practice SPICE simulations
3. How does a simulator work: Build your own simulator!
4. MOSFET modeling and short channel effects
5. Analog IC design automation and optimization
6. AMS behavioral modeling using Verilog-A
7. PLL design and simulation (Project)
8. Advanced topics in circuit simulation
01: Introduction 73
Course Prerequisites
❑ I expect you have taken undergraduate courses on
▪ Electronic devices (MOSFET models and operation)
▪ Electronic circuits
▪ Analog IC design
▪ Digital IC design
❑ If you didn’t study analog IC design before, then you MUST study this course on your own
▪ https://www.master-micro.com/mastering-microelectronics/courses/analog-ic-design
❑ This overview on the electronics industry is also VERY useful
▪ https://maharatech.gov.eg/course/view.php?id=32
01: Introduction 74
Mastering Microelectronics
Electrical Circuits Semiconductor Physics
Introduction to Electronics
Analog IC Design Digital IC Design

Analog Integrated Systems
Design
RF Circuit Design
01: Introduction 75
What Tools Are We Going to Use?
❑ SPICE Simulations
▪ LTSpice, Tanner T-Spice, Eldo, AFS, etc.
❑ Coding
▪ Python, Octave, Matlab, etc.
❑ Systematic analog design
▪ Octave or Matlab
▪ ADT
❑ Verilog-A simulations
▪ Ex: Tanner T-Spice, Eldo, AFS, Spectre, etc.
❑ Many practical assignments and projects

▪ The best way to learn anything is by doing it!
01: Introduction 76
Prospective Careers
❑ Analog/Mixed-Signal/RF IC Designer
❑ Analog/Mixed-Signal QA Engineer
❑ Analog/Mixed-Signal Product Engineer
❑ Analog/Mixed-Signal Automation Engineer
❑ Analog/Mixed-Signal CAD Engineer
01: Introduction 77
References
❑ Documentation of simulation tools (HSPICE, LTSpice, PSpice, Spectre, etc.)
❑ Mikael Sahrling, Analog Circuit Simulators for Integrated Circuit Designers, 2021
❑ Adel Sedra and Gordon Roberts, SPICE, 1997.
❑ L. T. Pillage, R. A. Rohrer, and C. Visweswariah, Electronic Circuit and System Simulation
Methods, McGraw-Hill, 1995.
❑ Farid N. Najm, Circuit Simulation, 2010.
❑ C. Cheng, CSE245, UCSD.
❑ P. Jespers and B. Murmann, Systematic Design of Analog CMOS Circuits Using Pre-
Computed Lookup Tables, 2017.
❑ Ken Kundert, The Designer's Guide to SPICE and Spectre, 2003.
❑ Ken Kundert, The Designer's Guide to Verilog-AMS, 2004.
01: Introduction 78
Where to Get Information From?
❑ Textbooks
❑ Courses in top universities (including Ain Shams University ☺)
❑ MSc/PhD theses in top universities: Search Google and Proquest
❑ Journal papers
▪ Mainly IEEE journals and transactions + few other journals
▪ Only a few conferences have good quality
• Ex: ISSCC, CICC, VLSI Symp., ESSCIRC, ASSCC
▪ Check references and citations of good papers
▪ Review papers are especially useful
❑ Websites and Forums
▪ Ex: semiwiki, edaboard, designers-guide, LinkedIn, FB (ECE Knowledge Exchange and
VLSI Egypt), etc.
01: Introduction 79
01: Introduction 80
Feedback
❑ Don’t hesitate to send me feedback to improve the course quality.
❑ Avoid two common misconceptions
1. Feedback should NOT wait to the end of the course!
• It will be too late to improve anything!
• But anyway, you may still help next generations ☺
2. Feedback should NOT be always negative!
• Too much negative feedback leads to zero output!
• Too much positive feedback causes oscillation!
• Be balanced!
01: Introduction 81
What Students Say About this Course
“This is one of the rare extremely well-prepared courses I have registered. The slides cover a
lot of details and has a good number of examples. The content itself is very useful and gives
very good insight in how circuit simulators in general are built which is valuable not only for
design engineers, but for engineers seeking a career in EDA companies as well.”
“The weekly labs are much more beneficial in a practical sense than an exam could ever be.
The teaching flow is very intuitive and is done at great pace, with a lot of time given to
answering students’ questions.”
“I would highly recommend any student to take this course.”
“I liked the clear explanations, the very well prepared slides, and many of the selected topics,
which I believe were extremely useful.”
01: Introduction 82
‫م‬
َ ُْ ََ
Module 01
Dr. Hesham A. Omran

2. Moore’s Law
01: Introduction 84
Main Branches of Electronics
Electronics
Microelectronics Electronic Power

(IC Design) Systems Electronics
Analog IC Digital IC Embedded

Design Design Systems
01: Introduction 85
Analog vs Digital Signals
❑ Analog: continuous in time and amplitude
❑ Digital: discrete in time and amplitude
01: Introduction [Razavi, 2014] 86

Why Digital?
❑ Digital circuits are
▪ Less sensitive to noise (robust)
▪ Easier to store (digital memories)
▪ Easier to process (digital signal processing: DSP)
▪ Amenable to automated design
▪ Amenable to automated testing
▪ Easier to port from one technology to another
▪ Direct beneficiary of Moore’s law (down-scaling)
01: Introduction 87
Why Analog?
❑ All the physical signals in the world around us are analog
▪ Voice, light, temperature, pressure, etc.
❑ We (will) always need an “analog” interface circuit to connect between our physical world
and our digital electronics
Digital
Amplifier A/D processing
Transducer and storage
01: Introduction 88
Signal Processing Chain
Amp A/D
Transducers
Physical world
Digital
(sound, light,
Power Management processing
temperature,
and storage
pressure, etc.)
Amp D/A
01: Introduction 89
Electronic System Example: Wireless Transceiver
Rx Amp A/D
EM Waves
Digital
Power Management processing
and storage
Tx Amp D/A
01: Introduction 90
Electronic System Example: Mixed-Signal Hearing Aid
ΣΔ ΣΔ H-Bridge
DSP
A/D D/A Driver
AGC Decimation
Filter
01: Introduction [Y. Chiu, EECT 7327, UTD] 91

Why Analog?
Analog World
Phone Lines, Cables (CT, CA) Audio
(DSL, Cable Modem) (MP3, Hearing Aid)
Video
(Dig. Camera, LCD TV,
TFT Display)
E&M Waves Digital World
(Cellphone, Radio, Mechanical Transducers
GPS) (DT, DA) (Car/Airplane Sensors,
MEMS, Nanopore)
Biochemical Sensors
Digital Storage (Hazard detection, Drug
(DVD, Hard Disk, Flash) Delivery, Lab-on-a-Chip)
01: Introduction [Y. Chiu, EECT 7327, UTD] 92

Why Analog?
❑ High speed digital design is actually analog design!
❑ At low speeds, we may directly digitize the signal and perform the signal processing in the
digital domain.
❑ At high speeds, signal processing in the analog domain is much more energy efficient.
❑ The boundary between high and low speed has risen over time.

‫م‬
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Module 01
Dr. Hesham A. Omran

2. Moore’s Law
01: Introduction 95
What is an Integrated Circuit (IC)?
❑ Various circuit elements: transistors, capacitors, resistors, and even small inductances can
be integrated on one chip
01: Introduction 96
Discrete vs. Integrated Electronics
Circuits using discrete components Integrated circuit
01: Introduction 97
Integrated Circuit Components
❑ Transistors:
▪ Billions of tiny transistors can be integrated on the same chip
▪ SSI -> MSI -> LSI -> VLSI (Very Large Scale Integration): > 10,000 transistors
❑ Capacitors:
▪ Capacitors as large as 100s of pF can be integrated on-chip
▪ But they consume a lot of chip area → Use sparingly
❑ Resistors:
▪ Resistors as large as few MOhms can be integrated on-chip
▪ But they consume a lot of chip area → Use sparingly
❑ Inductors:
▪ Small inductors (few nH) can be integrated on-chip
▪ But they consume a lot of area with relatively poor performance → Use sparingly: Only
in high frequency circuits (e.g., RFICs)
01: Introduction 98
IC Technology Generations
❑ Early integrated circuits primarily used bipolar transistors (BJTs)
❑ 1960s: MOS ICs became attractive for their low cost
▪ MOS transistor occupied less area
▪ The fabrication process was simpler
▪ Early commercial processes used only PMOS transistors and suffered from poor
performance, yield, and reliability
❑ 1970s: Processes using only NMOS transistors became common
01: Introduction 99
IC Technology Generations (Cont’d)
❑ Digital circuits in all the previous technologies have quiescent power consumption
▪ Power is dissipated when the circuit is idle, i.e., not switching
▪ This limits the maximum number of transistors that can be integrated on one die
01: Introduction 100

❑ 1980s: The VLSI era
▪ Power consumption became a major issue
▪ CMOS processes were widely adopted and replaced NMOS and bipolar processes for
nearly all digital logic applications
▪ A key advantage for “digital” CMOS is that it has negligible idle (static) power
consumption

❑ Nowadays:
▪ With aggressive scaling and billions of transistors, CMOS idle leakage current is not
negligible any more
▪ But no better technology is available yet…

Why CMOS?
❑ CMOS technologies dominated the digital market since the 1980s
→ CMOS = Complementary MOS = NMOS + PMOS
1. Consumed negligible static power
• Was indeed negligible in the past
• But not negligible any more…
2. Required very few devices per gate
3. Can be scaled down more easily
4. Lower fabrication cost
❑ For analog design, BJTs used to be much better than MOSFETs
▪ Faster, less noisy, less variations, more energy efficient
❑ Then why analog CMOS?
04: MOSFET DC 103

Why Analog CMOS?
❑ ICs market is driven primarily by memories and
microprocessors
▪ The analog designer needs to survive in a digital driven
market
❑ We want to integrate analog and digital on the same chip
▪ Mixed-signal design and system-on-a-chip
❑ BJTs used to be faster, but with continuous scaling,
MOSFET speed exceeded BJT
❑ MOSFET can operate with lower supply voltage
04: MOSFET DC [TECHCET CA LLC, Semiconductor Industry Market Trends 2019-20] 104
Analog Design Challenges
❑ Device scaling
▪ Transistors become faster, but the gain declines
❑ Supply voltage scaling
▪ From 12V in 1970s to less than 1V nowadays
❑ Low power consumption
▪ Increase battery lifetime, decrease cost and heat emissions
❑ Complexity
▪ Continuous increase in transistor count and system complexity
❑ PVT variations
▪ Tolerate large process, voltage, and temperature variations
❑ New applications
▪ Wireless standards, wearables, IoT, serial links (e.g., USB), power management

Analog Design Challenges
❑ In digital we have PPA
❑ In analog, we need to worry about many more things
▪ Analog design automation is a difficult task

‫م‬
َ ُْ ََ
Module 01
Dr. Hesham A. Omran

2. Moore’s Law

How to Design a Billion Transistor Chip?
1. Abstraction
▪ Hiding details until they become necessary
2. Structured design
▪ Hierarchy: Block, sub-blocks, … → Tree structure (from root to leaf cells)
▪ Regularity: Min no. of different blocks → Block reuse (e.g., standard cells)
▪ Modularity: Blocks are black boxes that have well-defined interfaces → Combine to
build larger system without surprises!
3. CAD Tools
▪ Automation, automation, automation!
▪ Analog automation is way behind digital automation

1. Abstraction
3. CAD Tools

Design Abstraction
1. Architecture design
▪ E.g., instruction set, register set, and memory model
▪ E.g., Intel x86 microprocessor architecture
2. Microarchitecture design
▪ Intel 8086, Pentium, Pentium II, …, Core i7 are all different implementations of x86
architecture
3. Logic Design
▪ E.g., a 32-bit adder can be ripple carry, carry lookahead, etc.
4. Circuit Design
▪ E.g., static CMOS, dynamic logic, pass-transistor logic, etc.
5. Physical Design
▪ Layout of transistors

Design Abstraction
01: Introduction [Rabaey, 2003] 112

Design Abstraction

1. Abstraction
▪ Hierarchy: Blocks, sub-blocks, … → Tree structure (from root to leaf cells)
3. CAD Tools

Structured Design: Modularity
❑ Which DFF preserves modularity?

1. Abstraction
3. CAD Tools

‫م‬
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Module 01
Dr. Hesham A. Omran

2. Moore’s Law

1. Abstraction
3. CAD Tools

CAD/EDA
❑ CAD: Computer aided design
❑ EDA: Electronic design automation
❑ CAD tools and EDA companies
❑ EDA activities started in academia and internally in big semiconductor companies (e.g., HP
and intel)
❑ EDA industry started in the 1980s

CAD/EDA
❑ Analog design
▪ Design entry (netlists and schematics), simulation, layout, and extraction
▪ Verification (LVS: layout vs schematic, DRC: layout design rule check)
❑ Digital design
▪ Design entry (e.g., HDL) and simulation
▪ Automated synthesis (from HDL to gates)
▪ Automated place and route (from gates to transistor layout)
▪ Verification
❑ System design
▪ Behavioral modeling and high-level simulation/verification
❑ EM simulation, process simulation, device simulation, etc.

EDA Market
❑ Software subscription model: very high renewal rates and loyalty
01: Introduction [Source: Synopsys, 2019] 122

Big EDA Players
Rank Company Revenue (2019) Employees (2019) Founded
#1 Synopsys $3.4 billion 13k 1986
#2 Cadence $2.3 billion 8k 1988
#3 Mentor > $1.3 billion (2017) > 6k (2017) 1981
❑ Big fish eat little fish

▪ Synopsys acquired Magma in 2011 for $507 million
▪ Cadence acquired Tensilica in 2013 for $380 million
▪ Mentor acquired Tanner in 2015 for ?? (undisclosed)
▪ Mentor acquired Solido in 2017 for ?? (undisclosed)
▪ …
Example: Cadence Market Breakdown
❑ Cadence revenue mix for 2020
01: Introduction [Cadence Report, 2020] 124

Big Fish “try to” Eat Big Fish?!

Big Fish Got Eaten by Bigger Fish!

Examples of EDA Tools
Synopsys Cadence Mentor (Siemens)
Schematic / Layout Custom Compiler Virtuoso Pyxis
Tanner S-Edit / L-Edit
SPICE Circuit Simulation HSPICE Spectre Eldo / Tanner T-Spice
Fast SPICE PrimeSim Spectre FX AFS

Waveform Viewer Custom WaveView Virtuoso Visualization EZ Wave
AMS Simulation CustomExplorer Ultra Virtuoso AMS Designer Questa ADMS
Analysis Environment Custom Explorer Analog Design ICanalyst
Environment
DRC / LVS IC Validator Assura/PVS Calibre nmDRC
Calibre nmLVS
Parasitic Extraction StarRC Quantus Calibre xRC
Digital P&R IC Compiler Encounter Aprisa
‫م‬
َ ُْ ََ
Module 01
Dr. Hesham A. Omran

2. Moore’s Law

Analog IC Design Flow (Simplified)
Design Specs
Topology Selection Fabrication
Circuit Hand Calculations

Packaging
Design and Analysis Tape-out
Simulation and
Testing
Design Adjustment
Physical Layout and Post No Specs

Design Layout Simulation met?
Yes
Specs
No met? Yes Product
01: Introduction [M. El-Nozahi, ASU] 130

Tape-Out
❑ The layout is sent to the fab in a format called GDS II
▪ Previously it was sent on a magnetic tape → tape-out
▪ Now by email (small design) or FTP (large design)

Tape-Out
❑ ICs are fabricated on silicon wafers
▪ Turnaround time ~ 3months
❑ A fabrication run in 65nm process costs about $3 million
▪ Cost sharing using MPW (multi-project wafer)
• US: MOSIS
• Europe and MENA: Europractice

MPW Example
❑ Link: http://www.europractice-ic.com/general_runschedule.php
❑ Foundries include TSMC, UMC, GLOBALFOUNDRIES, etc.
❑ < 50 samples only!

Packaging and Testing
❑ Wafer diced into dies
❑ Gold bond wires from die I/O pads to package
❑ Packaging is now much more advanced than
the simple DIP

Assignments
❑ Read
▪ IRDS 2020 Executive Summary: Section 1.2 (The New Ecosystem of The Electronics’
Industry)
❑ Watch
▪ Overview on the electronics industry
• https://maharatech.gov.eg/course/view.php?id=32
❑ Answer
▪ Assignment 01
▪ Quiz 01

Thank you!

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‫ن ا ْلعِْلِم إِاَّل قَلِ ًيل‬ِ ‫وما أُوتِيتم‬

Analog/Mixed-Signal Simulation and Modeling

Dr. Hesham A. Omran

ENIAC, U.S. Army, 1946 Smart phone

First transistor Trigate Transistor

First IC Quad-core CPU

01: Introduction [P. Gargini, IRDS, Intel] 9

❑ Ex: Do the following Google Search

Yellow: Solutions being pursued Red: No known solutions (yet)

01: Introduction [Tsu‐Jae King Liu, Berkeley, 2012] 11

Analog/Mixed-Signal Simulation and Modeling

Dr. Hesham A. Omran

“The complexity for minimum component costs has

[Gordon Moore, Electronics Magazine, 1965]

01: Introduction [Weste and Harris, 2010] 15

01: Introduction [Weste and Harris, 2010] 16

nMOS transistor pMOS transistor

Analog/Mixed-Signal Simulation and Modeling

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01: Introduction [Wolfgang Arden et. al., ITRS] 22

01: Introduction [Weste and Harris, 2010] 24

ADT at UCL [https://irds.ieee.org/images/files/pdf/2020/2020IRDS_BC.pdf] 27

01: Introduction [https://www.anandtech.com/show/16656/ibm-creates-first-2nm-chip] 29

01: Introduction [IRDS ES, 2020] 30

01: Introduction [IRDS ES, 2020] 31

ADT at UCL [https://irds.ieee.org/images/files/pdf/2020/2020IRDS_BC.pdf] 32

01: Introduction [P. Gargini, IRDS, Intel] 33

01: Introduction [Wolfgang Arden et. al., ITRS] 34

01: Introduction [https://nhanced-semi.com/technology/about-3d-ics/] 35

01: Introduction [Wolfgang Arden et. al., ITRS] 38

01: Introduction [IRDS, BC, 2017] 39

Analog/Mixed-Signal Simulation and Modeling

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01: Introduction [Weste and Harris, 2010] 42

Analog/Mixed-Signal Simulation and Modeling

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01: Introduction [SIA Beyond Borders Report, 2016] 55

01: Introduction [SIA Beyond Borders Report, 2016] 56

01: Introduction [SIA Beyond Borders Report, 2016] 57

Microelectronics Careers [https://www.icinsights.com/news/bulletins/Intel-To-Keep-Its-Number-One-Semiconductor-Supplier-Ranking-In-2020/] 58

01: Introduction [https://www.statista.com/statistics/266973/global-semiconductor-sales-since-1988/] 61

01: Introduction [Source: Synopsys, 2019] 62

01: Introduction [Source: Cadence, 2017] 63

01: Introduction [https://edition.cnn.com/interactive/2019/09/business/samsung-headquarters-south-korea/index.html] 65

01: Introduction [Synopsys, 2019] 66

01: Introduction [Vincent Roche, ADI, ISSCC Plenary Talk, 2018] 67

01: Introduction [Vincent Roche, ADI, ISSCC Plenary Talk, 2018] 68

Analog/Mixed-Signal Simulation and Modeling

Dr. Hesham A. Omran

2. Understand and practice SPICE simulations

3. How does a simulator work: Build your own simulator!

4. MOSFET modeling and short channel effects

5. Analog IC design automation and optimization

6. AMS behavioral modeling using Verilog-A

7. PLL design and simulation (Project)

8. Advanced topics in circuit simulation

Analog IC Design Digital IC Design

Analog/Mixed-Signal Simulation and Modeling

❑ Many practical assignments and projects

“I would highly recommend any student to take this course.”

Analog/Mixed-Signal Simulation and Modeling

Dr. Hesham A. Omran

Microelectronics Electronic Power