a Precision

Instrumentation Amplifier
AD524
FEATURES FUNCTIONAL BLOCK DIAGRAM
Low Noise: 0.3 ␮V p-p 0.1 Hz to 10 Hz
Low Nonlinearity: 0.003% (G = 1) –INPUT PROTECTION
High CMRR: 120 dB (G = 1000)
4.44kV AD524
Low Offset Voltage: 50 ␮V G = 10
Low Offset Voltage Drift: 0.5 ␮V/ⴗC G = 100
404V
Vb
Gain Bandwidth Product: 25 MHz 40V 20kV
SENSE
G = 1000
Pin Programmable Gains of 1, 10, 100, 1000
20kV 20kV
Input Protection, Power On–Power Off RG1
VOUT
No External Components Required RG2
20kV
20kV
Internally Compensated 20kV
REFERENCE
MIL-STD-883B and Chips Available
+INPUT PROTECTION
16-Lead Ceramic DIP and SOIC Packages and
20-Terminal Leadless Chip Carriers Available
Available in Tape and Reel in Accordance
with EIA-481A Standard
Standard Military Drawing Also Available

PRODUCT DESCRIPTION PRODUCT HIGHLIGHTS

The AD524 is a precision monolithic instrumentation amplifier 1. The AD524 has guaranteed low offset voltage, offset voltage
designed for data acquisition applications requiring high accu- drift and low noise for precision high gain applications.
racy under worst-case operating conditions. An outstanding 2. The AD524 is functionally complete with pin programmable
combination of high linearity, high common mode rejection, low gains of 1, 10, 100 and 1000, and single resistor program-
offset voltage drift and low noise makes the AD524 suitable for mable for any gain.
use in many data acquisition systems.
3. Input and output offset nulling terminals are provided for
The AD524 has an output offset voltage drift of less than 25 µV/°C, very high precision applications and to minimize offset volt-
input offset voltage drift of less than 0.5 µV/°C, CMR above age changes in gain ranging applications.
90 dB at unity gain (120 dB at G = 1000) and maximum non-
linearity of 0.003% at G = 1. In addition to the outstanding dc 4. The AD524 is input protected for both power-on and power-
specifications, the AD524 also has a 25 kHz gain bandwidth off fault conditions.
product (G = 1000). To make it suitable for high speed data 5. The AD524 offers superior dynamic performance with a gain
acquisition systems the AD524 has an output slew rate of 5 V/µs bandwidth product of 25 MHz, full power response of 75 kHz
and settles in 15 µs to 0.01% for gains of 1 to 100. and a settling time of 15 µs to 0.01% of a 20 V step (G = 100).
As a complete amplifier the AD524 does not require any exter-
nal components for fixed gains of 1, 10, 100 and 1000. For
other gain settings between 1 and 1000 only a single resistor is
required. The AD524 input is fully protected for both power-on
and power-off fault conditions.
The AD524 IC instrumentation amplifier is available in four
different versions of accuracy and operating temperature range.
The economical “A” grade, the low drift “B” grade and lower
drift, higher linearity “C” grade are specified from –25°C to
+85°C. The “S” grade guarantees performance to specification
over the extended temperature range –55°C to +125°C. Devices
are available in 16-lead ceramic DIP and SOIC packages and a
20-terminal leadless chip carrier.

REV. E
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 1999
AD524–SPECIFICATIONS (@ V = ⴞ15 V, R = 2 k⍀ and T = +25ⴗC unless otherwise noted)
S L A

AD524A AD524B AD524C AD524S

Model Min Typ Max Min Typ Max Min Typ Max Min Typ Max Units
GAIN
Gain Equation  40 , 000   40 , 000   40 , 000   40 , 000 
(External Resistor Gain  + 1 ± 20%  + 1 ± 20%  + 1 ± 20%  + 1 ± 20%
Programming)  RG   RG   RG   RG 
Gain Range (Pin Programmable) 1 to 1000 1 to 1000 1 to 1000 1 to 1000
Gain Error1
G=1 ⴞ0.05 ⴞ0.03 ⴞ0.02 ⴞ0.05 %
G = 10 ⴞ0.25 ⴞ0.15 ⴞ0.1 ⴞ0.25 %
G = 100 ⴞ0.5 ⴞ0.35 ⴞ0.25 ⴞ0.5 %
G = 1000 ±2.0 ⴞ1.0 ⴞ0.5 ⴞ2.0 %
Nonlinearity
G=1 ±0.01 ± 0.005 ± 0.003 ± 0.01 %
G = 10,100 ±0.01 ± 0.005 ± 0.003 ± 0.01 %
G = 1000 ±0.01 ± 0.01 ± 0.01 ± 0.01 %
Gain vs. Temperature
G=1 5 5 5 5 ppm/°C
G = 10 15 10 10 10 ppm/°C
G = 100 35 25 25 25 ppm/°C
G = 1000 100 50 50 50 ppm/°C
VOLTAGE OFFSET (May be Nulled)
Input Offset Voltage 250 100 50 100 µV
vs. Temperature 2 0.75 0.5 2.0 µV/°C
Output Offset Voltage 5 3 2.0 3.0 mV
vs. Temperature 100 50 25 50 µV/°C
Offset Referred to the
Input vs. Supply
G=1 70 75 80 75 dB
G = 10 85 95 100 95 dB
G = 100 95 105 110 105 dB
G = 1000 100 110 115 110 dB
INPUT CURRENT
Input Bias Current ⴞ50 ⴞ25 ⴞ15 ⴞ50 nA
vs. Temperature ±100 ±100 ± 100 ± 100 pA/°C
Input Offset Current ⴞ35 ⴞ15 ⴞ10 ⴞ35 nA
vs. Temperature ±100 ±100 ± 100 ± 100 pA/°C
INPUT
Input Impedance
Differential Resistance 109 10 9 10 9 10 9 Ω
Differential Capacitance 10 10 10 10 pF
Common-Mode Resistance 109 10 9 10 9 10 9 Ω
Common-Mode Capacitance 10 10 10 10 pF
Input Voltage Range
Max Differ. Input Linear (V DL) 2 ±10 ±10 ± 10 ± 10 V
G  G  G  G 
Max Common-Mode Linear (V CM) 12 V –  × VD  12 V –  × VD  12 V –  × VD  12 V –  × VD  V
 2   2   2   2 
Common-Mode Rejection dc to
60 Hz with 1 kΩ Source Imbalance
G=1 70 75 80 70 dB
G = 10 90 95 100 90 dB
G = 100 100 105 110 100 dB
G = 1000 110 115 120 110 dB
OUTPUT RATING
VOUT, RL = 2 kΩ ±10 ±10 ± 10 ± 10 V
DYNAMIC RESPONSE
Small Signal – 3 dB
G=1 1 1 1 1 MHz
G = 10 400 400 400 400 kHz
G = 100 150 150 150 150 kHz
G = 1000 25 25 25 25 kHz
Slew Rate 5.0 5.0 5.0 5.0 V/µs
Settling Time to 0.01%, 20 V Step
G = 1 to 100 15 15 15 15 µs
G = 1000 75 75 75 75 µs
NOISE
Voltage Noise, 1 kHz
R.T.I. 7 7 7 7 nV/√Hz
R.T.O. 90 90 90 90 nV√Hz
R.T.I., 0.1 Hz to 10 Hz
G=1 15 15 15 15 µV p-p
G = 10 2 2 2 2 µV p-p
G = 100, 1000 0.3 0.3 0.3 0.3 µV p-p
Current Noise
0.1 Hz to 10 Hz 60 60 60 60 pA p-p

–2– REV. E
 AD524
AD524A AD524B AD524C AD524S
Model Min Typ Max Min Typ Max Min Typ Max Min Typ Max Units

SENSE INPUT
RIN 20 20 20 20 kΩ ±20%
IIN 15 15 15 15 µA
Voltage Range ±10 ±10 ±10 ±10 V
Gain to Output l l 1 l %

REFERENCE INPUT
RIN 40 40 40 40 kΩ ±20%
IIN 15 15 15 15 µA
Voltage Range ±10 ±10 10 10 V
Gain to Output l 1 l 1 %

TEMPERATURE RANGE
Specified Performance –25 +85 –25 +85 –25 +85 –55 +125 °C
Storage –65 +150 –65 +150 –65 +150 –65 +150 °C

POWER SUPPLY
Power Supply Range ⴞ6 ±15 ⴞ18 ⴞ6 ±15 ⴞ18 ⴞ6 ±15 ⴞ18 ⴞ6 ±15 ⴞ18 V
Quiescent Current 3.5 5.0 3.5 5.0 3.5 5.0 3.5 5.0 mA
NOTES
1
Does not include effects of external resistor RG.
2
VOL is the maximum differential input voltage at G = 1 for specified nonlinearity.
VDL at the maximum = 10 V/G.
VD = Actual differential input voltage.
Example: G = 10, VD = 0.50.
VCM = 12 V – (10/2 × 0.50 V) = 9.5 V.
Specification subject to change without notice.
All min and max specifications are guaranteed. Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to
calculate outgoing quality levels.

REV. E –3–
AD524
ABSOLUTE MAXIMUM RATINGS l CONNECTION DIAGRAMS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . . 450 mW Ceramic (D) and
Input Voltage2 SOIC (R) Packages
(Either Input Simultaneously) |VIN| + |VS | . . . . . . . . <36 V
Output Short Circuit Duration . . . . . . . . . . . . . . . . . Indefinite – INPUT 1 16 RG1

Storage Temperature Range + INPUT 2 15 OUTPUT NULL

(R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +125°C RG2 3 14 OUTPUT NULL
(D, E) . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C INPUT NULL 4 AD524 13 G = 10 SHORT TO
TOP VIEW
Operating Temperature Range INPUT NULL 5 (Not to Scale) 12 G = 100
RG2 FOR
DESIRED
AD524A/B/C . . . . . . . . . . . . . . . . . . . . . . . . –25°C to +85°C REFERENCE 6 11 G = 1000 GAIN
AD524S . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C –VS 7 10 SENSE
Lead Temperature (Soldering 60 secs) . . . . . . . . . . . . +300°C +VS 8 9 OUTPUT
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent 4 15
damage to the device. This is a stress rating only; functional operation of the device at +VS –VS
these or any other conditions above those indicated in the operational section of this
INPUT 5 14 OUTPUT
specification is not implied. Exposure to absolute maximum rating conditions for
OFFSET NULL OFFSET NULL
extended periods may affect device reliability.
2
Max input voltage specification refers to maximum voltage to which either input
terminal may be raised with or without device power applied. For example, with ± 18
volt supplies max V IN is ± 18 volts, with zero supply voltage max V IN is ± 36 volts.
Leadless Chip Carrier
METALIZATION PHOTOGRAPH
Contact factory for latest dimensions.

OUTPUT
+INPUT
–INPUT
Dimensions shown in inches and (mm).

NULL
RG1
NC
OUTPUT
NULL G = 10 G = 100 G = 1000 SENSE 3 2 1 20 19
14 13 12 11 10

OUTPUT RG2 4 18 OUTPUT NULL

15
NULL 9 OUTPUT INPUT NULL 5 17 G = 10 SHORT TO
AD524 16 NC RG2 FOR
RG1 16 8 +VS NC 6
TOP VIEW DESIRED
INPUT NULL 7 15 G = 100
8 14 G = 1000 GAIN
0.103 REFERENCE
(2.61)
9 10 11 12 13
–INPUT 1 –VS NC = NO CONNECT
+VS
NC
OUTPUT
SENSE
+INPUT 2 7 –VS
RG2 3
7 19
4 5 6
INPUT INPUT REFERENCE +VS –VS
NULL NULL INPUT 5 18 OUTPUT
0.170 (4.33) OFFSET NULL OFFSET NULL
PAD NUMBERS CORRESPOND TO PIN NUMBERS FOR THE
D-16 AND R-16 16-PIN CERAMIC PACKAGES.

ORDERING GUIDE

Model Temperature Ranges Package Descriptions Package Options

AD524AD –40°C to +85°C 16-Lead Ceramic DIP D-16
AD524AE –40°C to +85°C 20-Terminal Leadless Chip Carrier E-20A
AD524AR-16 –40°C to +85°C 16-Lead Gull-Wing SOIC R-16
AD524AR-16-REEL –40°C to +85°C Tape & Reel Packaging 13"
AD524AR-16-REEL7 –40°C to +85°C Tape & Reel Packaging 7"
AD524BD –40°C to +85°C 16-Lead Ceramic DIP D-16
AD524BE –40°C to +85°C 20-Terminal Leadless Chip Carrier E-20A
AD524CD –40°C to +85°C 16-Lead Ceramic DIP D-16
AD524SD –55°C to +125°C 16-Lead Ceramic DIP D-16
AD524SD/883B –55°C to +125°C 16-Lead Ceramic DIP D-16
5962-8853901EA* –55°C to +125°C 16-Lead Ceramic DIP D-16
AD524SE/883B –55°C to +125°C 20-Terminal Leadless Chip Carrier E-20A
AD524SCHIPS –55°C to +125°C Die
*
Refer to official DESC drawing for tested specifications.

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. WARNING!
Although the AD524 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
ESD SENSITIVE DEVICE
precautions are recommended to avoid performance degradation or loss of functionality.

–4– REV. E
 AD524–Typical Characteristics
20 20 30

OUTPUT VOLTAGE SWING – Vp-p

OUTPUT VOLTAGE SWING – 6V
INPUT VOLTAGE – 6V

15 15
20

10 10

+258C
10
5 5

0 0 0
0 5 10 15 20 0 5 10 15 20 10 100 1k 10k
SUPPLY VOLTAGE – 6V SUPPLY VOLTAGE – 6V LOAD RESISTANCE – V

Figure 1. Input Voltage Range vs. Figure 2. Output Voltage Swing vs. Figure 3. Output Voltage Swing vs.
Supply Voltage, G = 1 Supply Voltage Load Resistance

8.0 16 40

14 30

INPUT BIAS CURRENT – nA

INPUT BIAS CURRENT – 6nA
QUIESCENT CURRENT – mA

6.0 12 20

10 10

4.0 8 0

6 –10

2.0 4 –20

2 –30

0 0 –40
0 5 10 15 20 0 5 10 15 20 –75 –25 25 75 125
SUPPLY VOLTAGE – 6V SUPPLY VOLTAGE – 6V TEMPERATURE – 8C

Figure 4. Quiescent Current vs. Figure 5. Input Bias Current vs. Figure 6. Input Bias Current vs.
Supply Voltage Supply Voltage Temperature

16

14 0
INPUT BIAS CURRENT – 6nA

DVOS FROM FINAL VALUE – mV

12 1
1000
10 2
GAIN – V/V

100
8 3
10
6 4

4 5 1

2 6

0
0 5 10 15 20 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 0 10 100 1k 10k 100k 1M 10M
INPUT VOLTAGE – 6V WARM-UP TIME – Minutes FREQUENCY – Hz

Figure 7. Input Bias Current vs. Input Figure 8. Offset Voltage, RTI, Turn Figure 9. Gain vs. Frequency
Voltage On Drift

REV. E –5–
AD524
–140 30 10.0
G = 1000
G = 100

FULL POWER RESPONSE – Vp-p

–120
G = 1, 10, 100 8.0
G = 10
–100

SLEW RATE –V/ms

20
CMRR – dB

G=1 6.0
–80

–60 4.0
10
–40 G = 1000
2.0
BANDWIDTH LIMITED
–20
G1000 G100 G10
0 0 0
0 10 100 1k 10k 100k 1M 10M 1k 10k 100k 1M 1 10 100 1000
FREQUENCY – Hz FREQUENCY – Hz GAIN – V/V

Figure 10. CMRR vs. Frequency RTI, Figure 11. Large Signal Frequency Figure 12. Slew Rate vs. Gain
Zero to 1k Source Imbalance Response

160 160 1000

–VS = –15V dc +
+VS = 15V dc +
POWER SUPPLY REJECTION – dB
POWER SUPPLY REJECTION – dB

140 140 1V p-p SINEWAVE

1V p-p SINEWAVE
120 100 G=1
120

VOLT NSD – nV/ Hz

G= G=
100 100 100 100
0 0 G = 10
G= G=
100 100
80 G= 80 10
G= G = 100, 1000
10 10
60 60
G= G= G = 1000
1 1
40 40 1

20 20

0 0 0.1
10 100 1k 10k 100k 10 100 1k 10k 100k 1 10 100 1k 10k 100k
FREQUENCY – Hz FREQUENCY – Hz FREQUENCY – Hz

Figure 13. Positive PSRR vs. Figure 14. Negative PSRR vs. Figure 15. RTI Noise Spectral
Frequency Frequency Density vs. Gain

0.1 – 10Hz 0.1 – 10Hz

CURRENT NOISE SPECTRAL DENSITY – fA/ Hz

100k

10k

1000

100

VERTICAL SCALE; 1 DIVISION = 5mV VERTICAL SCALE; 1 DIVISION = 0.1mV

0 1 10 100 1k 10k
FREQUENCY – Hz

Figure 16. Input Current Noise vs. Figure 17. Low Frequency Noise␣ – Figure 18. Low Frequency Noise –
Frequency G = 1 (System Gain = 1000) G = 1000 (System Gain = 100,000)

–6– REV. E
 AD524
–12 TO +12 –12 TO +12
1% 0.1% 0.01% 1% 0.1% 0.01%
–8 TO +8 –8 TO +8

–4 TO +4 –4 TO +4
OUTPUT OUTPUT
STEP – V STEP – V
+4 TO –4 +4 TO –4

+8 TO –8 +8 TO –8
1% 0.1% 0.01% 1% 0.1% 0.01%
+12 TO –12 +12 TO –12

0 5 10 15 20 0 5 10 15 20
SETTLING TIME – ms SETTLING TIME – ms

Figure 19. Settling Time Gain = 1 Figure 20. Large Signal Pulse Figure 21. Settling Time Gain = 10
Response and Settling Time – G =1

–12 TO +12
0.1%
1% 0.01%
–8 TO +8

–4 TO +4

OUTPUT
STEP – V
+4 TO –4

+8 TO –8
1% 0.01%
+12 TO –12 0.1%

0 5 10 15 20
SETTLING TIME – ms

Figure 22. Large Signal Pulse Figure 23. Settling Time Gain = 100 Figure 24. Large Signal Pulse
Response and Settling Time Response and Settling Time
G = 10 G = 100

–12 TO +12
1% 0.1% 0.01%
–8 TO +8

–4 TO +4

OUTPUT
STEP – V
+4 TO –4

+8 TO –8
1% 0.1% 0.01%
+12 TO –12

0 10 20 30 40 50 60 70 80
SETTLING TIME – ms

Figure 25. Settling Time Gain = 1000 Figure 26. Large Signal Pulse Re-
sponse and Settling Time G = 1000

REV. E –7–
AD524
10kV 1kV 10kV As RG is reduced to increase the programmed gain, the trans-
0.01% 10T 0.1% conductance of the input preamp increases to the transconduct-
INPUT VOUT ance of the input transistors. This has three important advantages.
20V p-p 100kV +VS
0.1% First, this approach allows the circuit to achieve a very high
RG1
open loop gain of 3 × 108 at a programmed gain of 1000, thus
G = 10
reducing gain-related errors to a negligible 30 ppm. Second, the
G = 100
11kV 1kV 100V G = 1000
AD524 gain bandwidth product, which is determined by C3 or C4 and
0.1% 0.1% 0.1%
RG2
the input transconductance, reaches 25 MHz. Third, the input
voltage noise reduces to a value determined by the collector
current of the input transistors for an RTI noise of 7 nV/√Hz at
–VS G = 1000.
Figure 27. Settling Time Test Circuit
INPUT PROTECTION
As interface amplifiers for data acquisition systems, instrumen-
+VS
tation amplifiers are often subjected to input overloads, i.e.,
voltage levels in excess of the full scale for the selected gain
I1 VB
I2 range. At low gains, 10 or less, the gain resistor acts as a current
50mA 50mA
limiting element in series with the inputs. At high gains the
R52
lower value of RG will not adequately protect the inputs from
A1 A2 20kV excessive currents. Standard practice would be to place series
R53 SENSE
C3 C4 20kV limiting resistors in each input, but to limit input current to
R57 A3 VO below 5 mA with a full differential overload (36 V) would re-
CH2,
CH3, CH4
20kV
R56 R54 quire over 7k of resistance which would add 10 nV√Hz of noise.
R55
–IN Q1, Q3 20kV Q2, Q4 20kV
20kV To provide both input protection and low noise a special series
4.44kV REFERENCE
CH1 CH2, CH3,
protect FET was used.
RG1 RG2
404V CH4
G100 +IN A unique FET design was used to provide a bidirectional cur-
I3 I4
50mA
40V
G1000 50mA CH1
rent limit, thereby, protecting against both positive and negative
overloads. Under nonoverload conditions, three channels CH2,
–VS
CH3, CH4, act as a resistance (≈1 kΩ) in series with the input as
before. During an overload in the positive direction, a fourth
Figure 28 Simplified Circuit of Amplifier; Gain Is Defined as channel, CH1, acts as a small resistance (≈3 kΩ) in series with
((R56 + R57)/(RG)) + 1. For a Gain of 1, RG Is an Open Circuit the gate, which draws only the leakage current, and the FET
limits IDSS . When the FET enhances under a negative overload,
the gate current must go through the small FET formed by CH1
Theory of Operation and when this FET goes into saturation, the gate current is
The AD524 is a monolithic instrumentation amplifier based on limited and the main FET will go into controlled enhancement.
the classic 3 op amp circuit. The advantage of monolithic con- The bidirectional limiting holds the maximum input current to
struction is the closely matched components that enhance the 3 mA over the 36 V range.
performance of the input preamp. The preamp section develops
the programmed gain by the use of feedback concepts. The INPUT OFFSET AND OUTPUT OFFSET
programmed gain is developed by varying the value of RG (smaller Voltage offset specifications are often considered a figure of
values increase the gain) while the feedback forces the collector merit for instrumentation amplifiers. While initial offset may be
currents Q1, Q2, Q3 and Q4 to be constant, which impresses adjusted to zero, shifts in offset voltage due to temperature
the input voltage across RG. variations will cause errors. Intelligent systems can often correct
for this factor with an autozero cycle, but there are many small-
signal high-gain applications that don’t have this capability.

+VS

AD712
10 +Vs
100 AD524 16.2kV
1mF
1000 DUT
1/2
RG2 1/2
1mF 9.09kV

1mF 16.2kV
G1, 10, 100
–VS G1000 –VS
1kV
100V
1.62MV 1.82kV

Figure 29. Noise Test Circuit

–8– REV. E
 AD524
Voltage offset and drift comprise two components each; input For best results RG should be a precision resistor with a low
and output offset and offset drift. Input offset is that component temperature coefficient. An external RG affects both gain accuracy
of offset that is directly proportional to gain i.e., input offset as and gain drift due to the mismatch between it and the internal
measured at the output at G = 100 is 100 times greater than at thin-film resistors. Gain accuracy is determined by the tolerance
G = 1. Output offset is independent of gain. At low gains, out- of the external RG and the absolute accuracy of the internal resis-
put offset drift is dominant, while at high gains input offset drift tors (±20%). Gain drift is determined by the mismatch of the
dominates. Therefore, the output offset voltage drift is normally temperature coefficient of RG and the temperature coefficient of
specified as drift at G = 1 (where input effects are insignificant), the internal resistors (– 50 ppm/°C typ).
while input offset voltage drift is given by drift specification at a
high gain (where output offset effects are negligible). All input- +VS
related numbers are referred to the input (RTI) which is to say –INPUT
that the effect on the output is “G” times larger. Voltage offset RG1
vs. power supply is also specified at one or more gain settings 1.5kV
and is also RTI. 2.105kV AD524 VOUT
1kV
By separating these errors, one can evaluate the total error inde- RG2 REFERENCE
pendent of the gain setting used. In a given gain configuration +INPUT 40,000 +1 = 20 620%
G=
both errors can be combined to give a total error referred to the –VS 2.105
input (R.T.I.) or output (R.T.O.) by the following formula:
Figure 31. Operating Connections for G = 20
Total Error R.T.I. = input error + (output error/gain)
The second technique uses the internal resistors in parallel with
Total Error R.T.O. = (Gain × input error) + output error
an external resistor (Figure 32). This technique minimizes the
As an illustration, a typical AD524 might have a +250 µV out- gain adjustment range and reduces the effects of temperature
put offset and a –50 µV input offset. In a unity gain configura- coefficient sensitivity.
tion, the total output offset would be 200 µV or the sum of the
two. At a gain of 100, the output offset would be –4.75 mV or: +VS
+250 µV + 100(–50 µV) = –4.75 mV. –INPUT
RG1
The AD524 provides for both input and output offset adjust-
G = 10
ment. This simplifies very high precision applications and mini- 4kV AD524 VOUT
mize offset voltage changes in switched gain applications. In
such applications the input offset is adjusted first at the highest RG2 REFERENCE
programmed gain, then the output offset is adjusted at G = 1. +INPUT
40,000
G= +1 = 20 617%
*R|G = 10 = 4444.44V –VS 4000||4444.44
GAIN *R|G = 100 = 404.04V
*R|G = 1000 = 40.04V
The AD524 has internal high accuracy pretrimmed resistors for
*NOMINAL (620%)
pin programmable gain of 1, 10, 100 and 1000. One of the
preset gains can be selected by pin strapping the appropriate Figure 32. Operating Connections for G = 20, Low Gain
gain terminal and RG2 together (for G = 1 RG2 is not connected). T.C. Technique

INPUT
The AD524 may also be configured to provide gain in the out-
+VS
OFFSET put stage. Figure 33 shows an H pad attenuator connected to
NULL
the reference and sense lines of the AD524. R1, R2 and R3
–INPUT 10kV
should be made as low as possible to minimize the gain variation
RG1
and reduction of CMRR. Varying R2 will precisely set the gain
G = 10
without affecting CMRR. CMRR is determined by the match of
G = 100 AD524 VOUT
G = 1000
R1 and R3.
RG2 OUTPUT
SIGNAL +VS
+INPUT R1
COMMON
–INPUT 2.26kV
–VS
RG1
G = 10 R2
Figure 30. Operating Connections for G = 100 5kV
G = 100 AD524 VOUT
The AD524 can be configured for gains other than those that G = 1000 RL
are internally preset; there are two methods to do this. The first RG2 R3
method uses just an external resistor connected between pins 3 +INPUT 2.26kV
and 16, which programs the gain according to the formula G=
(R2||40kV) + R1 + R3 –VS
(R2||40kV) (R1 + R2 + R3)||RL $ 2kV

40k
RG = Figure 33. Gain of 2000
G = –1

(see Figure 31).

REV. E –9–
AD524
Table I. Output Gain Resistor Values Although instrumentation amplifiers have differential inputs,
there must be a return path for the bias currents. If this is not
Output Nominal provided, those currents will charge stray capacitances, causing
Gain R2 R1, R3 Gain the output to drift uncontrollably or to saturate. Therefore,
when amplifying “floating” input sources such as transformers
2 5 kΩ 2.26 kΩ 2.02 and thermocouples, as well as ac-coupled sources, there must
5 1.05 kΩ 2.05 kΩ 5.01 still be a dc path from each input to ground.
10 1 kΩ 4.42 kΩ 10.1
COMMON-MODE REJECTION
INPUT BIAS CURRENTS Common-mode rejection is a measure of the change in output
Input bias currents are those currents necessary to bias the input voltage when both inputs are changed equal amounts. These
transistors of a dc amplifier. Bias currents are an additional specifications are usually given for a full-range input voltage
source of input error and must be considered in a total error change and a specified source imbalance. “Common-Mode
budget. The bias currents, when multiplied by the source resis- Rejection Ratio” (CMRR) is a ratio expression while “Common-
tance, appear as an offset voltage. What is of concern in calculat- Mode Rejection” (CMR) is the logarithm of that ratio. For
ing bias current errors is the change in bias current with respect to example, a CMRR of 10,000 corresponds to a CMR of 80 dB.
signal voltage and temperature. Input offset current is the differ- In an instrumentation amplifier, ac common-mode rejection is
ence between the two input bias currents. The effect of offset only as good as the differential phase shift. Degradation of ac
current is an input offset voltage whose magnitude is the offset common-mode rejection is caused by unequal drops across
current times the source impedance imbalance. differing track resistances and a differential phase shift due to
+VS varied stray capacitances or cable capacitances. In many appli-
cations shielded cables are used to minimize noise. This tech-
nique can create common mode rejection errors unless the
shield is properly driven. Figures 35 and 36 shows active data
AD524 guards that are configured to improve ac common mode rejec-
tion by “bootstrapping” the capacitances of the input cabling,
LOAD
thus minimizing differential phase shift.
–VS
TO POWER
+VS
SUPPLY
GROUND –INPUT

a. Transformer Coupled G = 100

100V
RG2 AD524 VOUT
+VS
AD711
+INPUT REFERENCE

–VS
AD524
Figure 35. Shield Driver, G ≥ 100
LOAD

–VS
TO POWER +VS
–INPUT
SUPPLY
GROUND AD712 RG1
100V
b. Thermocouple
AD524 VOUT

+VS –VS
100V RG2 REFERENCE

+INPUT
–VS
AD524
Figure 36. Differential Shield Driver
LOAD
GROUNDING
–VS Many data acquisition components have two or more ground
TO POWER
SUPPLY
GROUND
pins that are not connected together within the device. These
grounds must be tied together at one point, usually at the sys-
c. AC Coupled
tem power-supply ground. Ideally, a single solid ground would
Figure 34. Indirect Ground Returns for Bias Currents be desirable. However, since current flows through the ground
wires and etch stripes of the circuit cards, and since these paths
have resistance and inductance, hundreds of millivolts can be
generated between the system ground point and the data

–10– REV. E
 AD524
acquisition components. Separate ground returns should be REFERENCE TERMINAL
provided to minimize the current flow in the path from the sensi- The reference terminal may be used to offset the output by up
tive points to the system ground point. In this way supply currents to ± 10 V. This is useful when the load is “floating” or does not
and logic-gate return currents are not summed into the same share a ground with the rest of the system. It also provides a
return path as analog signals where they would cause measure- direct means of injecting a precise offset. It must be remem-
ment errors. bered that the total output swing is ±10 volts to be shared be-
Since the output voltage is developed with respect to the poten- tween signal and reference offset.
tial on the reference terminal, an instrumentation amplifier can When the IA is of the three-amplifier configuration it is neces-
solve many grounding problems. sary that nearly zero impedance be presented to the reference
terminal.
Any significant resistance from the reference terminal to ground
ANALOG P.S. DIGITAL P.S. increases the gain of the noninverting signal path, thereby upset-
+15V C –15V C +5V ting the common-mode rejection of the IA.
In the AD524 a reference source resistance will unbalance the
CMR trim by the ratio of 20 kΩ/RREF. For example, if the refer-
0.1 0.1 0.1 0.1
mF mF mF mF
1mF 1mF 1mF
ence source impedance is 1 Ω, CMR will be reduced to 86 dB
(20 kΩ/1 Ω = 86 dB). An operational amplifier may be used to
DIG
COM provide that low impedance reference point as shown in Figure
AD583 DIGITAL
39. The input offset voltage characteristics of that amplifier will
AD524
SAMPLE AD574A DATA add directly to the output offset voltage performance of the
AND HOLD OUTPUT
6 instrumentation amplifier.
*ANALOG
OUTPUT GROUND SIGNAL +VS
REFERENCE GROUND
*IF INDEPENDENT; OTHERWISE RETURN AMPLIFIER REFERENCE SENSE
TO MECCA AT ANALOG P.S. COMMON VIN +

Figure 37. Basic Grounding Practice AD524

REF LOAD
SENSE TERMINAL VIN –

The sense terminal is the feedback point for the instrument

–VS
amplifier’s output amplifier. Normally it is connected to the
VOFFSET
instrument amplifier output. If heavy load currents are to be AD711
drawn through long leads, voltage drops due to current flowing
Figure 39. Use of Reference Terminal to Provide Output
through lead resistance can cause errors. The sense terminal can
Offset
be wired to the instrument amplifier at the load, thus putting
the IxR drops “inside the loop” and virtually eliminating this An instrumentation amplifier can be turned into a voltage-to-
error source. current converter by taking advantage of the sense and reference
terminals as shown in Figure 40.
V+
(SENSE)
OUTPUT
VIN + CURRENT SENSE
BOOSTER +INPUT
R1
AD524 X1 AD524 IL
VX
RL
VIN – (REF)
–INPUT
REF
A2
V–
AD711
Figure 38. AD524 Instrumentation Amplifier with Output VX VIN 40,000
LOAD
Current Booster IL =
R1
=
R1
(
= 1+
RG
)
Typically, IC instrumentation amplifiers are rated for a full ± 10 Figure 40. Voltage-to-Current Converter
volt output swing into 2 kΩ. In some applications, however, the
need exists to drive more current into heavier loads. Figure 38 By establishing a reference at the “low” side of a current setting
shows how a high-current booster may be connected “inside the resistor, an output current may be defined as a function of input
loop” of an instrumentation amplifier to provide the required voltage, gain and the value of that resistor. Since only a small
current boost without significantly degrading overall perfor- current is demanded at the input of the buffer amplifier A2, the
mance. Nonlinearities, offset and gain inaccuracies of the buffer forced current IL will largely flow through the load. Offset and
are minimized by the loop gain of the IA output amplifier. Off- drift specifications of A2 must be added to the output offset and
set drift of the buffer is similarly reduced. drift specifications of the IA.

REV. E –11–
AD524

–IN 1 PROTECTION 16
OUTPUT G = 10 G = 100 G = 1000
OFFSET K1 K2 K3
+IN 2 PROTECTION 15 TRIM
R2 NC
+VS
10kV
3 14
INPUT
OFFSET 4.44kV
4 13
TRIM R1 RELAY
10kV 20kV 20kV 404V SHIELDS
5 12
20kV 20kV
20kV 40V
6 11

20kV +5V
–VS 7 10
A1 K1 D1 K2 D2 K3 D3
AD524 OUT
+VS 8 9

1mF C1 C2
35V
INPUTS A
ANALOG K1 – K3 = GAIN Y0
COMMON THERMOSEN DM2C RANGE B
4.5V COIL Y1
D1 – D3 = IN4148 74LS138 7407N
Y2 BUFFER
DECODER
GAIN TABLE DRIVER
10mF
A B GAIN
0 0 10 +5V
0 1 1000
1 0 100
1 1 1
LOGIC
NC = NO CONNECT COMMON

Figure 41. Three Decade Gain Programmable Amplifier

PROGRAMMABLE GAIN
(+INPUT)
Figure 41 shows the AD524 being used as a software program- –IN 1 PROTECTION 16
OUTPUT
mable gain amplifier. Gain switching can be accomplished with (–INPUT) OFFSET
+IN 2 PROTECTION 15 NULL
mechanical switches such as DIP switches or reed relays. It TO –V
+VS
should be noted that the “on” resistance of the switch in series 3 14 R2
10kV
with the internal gain resistor becomes part of the gain equation INPUT
4.44kV
OFFSET
and will have an effect on gain accuracy. NULL 4 13
10kV 20kV 20kV 404V
The AD524 can also be connected for gain in the output stage. 5 12
20kV 20kV
Figure 42 shows an AD711 used as an active attenuator in the 20kV 40V
6 11
output amplifier’s feedback loop. The active attenuation pre-
20kV
sents a very low impedance to the feedback resistors, therefore –VS 7 10
AD524
minimizing the common-mode rejection ratio degradation.
+VS 8 9 VOUT
1mF
35V 20kV

10pF
VSS VDD GND

+VS

39.2kV 1kV
AD711 28.7kV 1kV
–VS 316kV 1kV

AD7590

VDD A2 A3 A4 WR

Figure 42. Programmable Output Gain

–12– REV. E
 AD524
+VS
+INPUT
(–INPUT) 1 PROTECTION +INPUT
4.44kV RG1
G = 10 13 AD524
G = 10
404V
G = 100 12 Vb G = 100 AD524
20kV
40V 10
G = 1000 11 G = 1000
20kV 20kV RG2
RG1 16
9 VOUT –INPUT
RG2 3
20kV 20kV 39kV VREF –VS
6 –VS
20kV R3
–INPUT 2 AD589 +VS 20kV R5
PROTECTION 20kV
(+INPUT)
C1
MSB +VS
+VS 1/2
1/2 DATA OUT1 R4
17 3 AD712 INPUTS LSB 10kV AD712
AD7524
4 2 OUT2
DAC A CS
DATA 14 DB0 1/2
WR AD712 R6
INPUTS 7 DB7 256:1 5kV
1 –VS
CS 15
AD7528
WR 16 GND
19
DAC A/DAC B 6
18 DAC B 20 Figure 44. Software Controllable Offset
1/2
5 AD712
In many applications complex software algorithms for autozero
applications are not available. For those applications Figure 45
provides a hardware solution.
Figure 43. Programmable Output Gain Using a DAC
+VS
Another method for developing the switching scheme is to use a
DAC. The AD7528 dual DAC, which acts essentially as a pair 15 16 RG1 8
of switched resistive attenuators having high analog linearity and 10
VOUT
14
symmetrical bipolar transmission, is ideal in this application. AD524
13 9 10
The multiplying DAC’s advantage is that it can handle inputs of RG2 0.1mF LOW CH
LEAKAGE
either polarity or zero without affecting the programmed gain.
The circuit shown uses an AD7528 to set the gain (DAC A) and 1kV
to perform a fine adjustment (DAC B). –VS
12 11
AD711
AUTOZERO CIRCUITS
In many applications it is necessary to provide very accurate
VDD
data in high gain configurations. At room temperature the offset
VSS AD7510KD
effects can be nulled by the use of offset trimpots. Over the
GND
operating temperature range, however, offset nulling becomes a
problem. The circuit of Figure 44 show a CMOS DAC operat- A1 A2 A3 A4
200ms
ing in the bipolar mode and connected to the reference terminal ZERO PULSE
to provide software controllable offset adjustments.
Figure 45. Autozero Circuit

REV. E –13–
AD524
ERROR BUDGET ANALYSIS
To illustrate how instrumentation amplifier specifications are
applied, we will now examine a typical case where an AD524 is
required to amplify the output of an unbalanced transducer.
Figure 46 shows a differential transducer, unbalanced by 100 Ω,
supplying a 0 to 20 mV signal to an AD524C. The output of the
IA feeds a 14-bit A-to-D converter with a 0 to 2 volt input volt-
age range. The operating temperature range is –25°C to +85°C.
Therefore, the largest change in temperature ∆T within the
operating range is from ambient to +85°C (85°C – 25°C = 60°C).
In many applications, differential linearity and resolution are of
prime importance. This would be so in cases where the absolute
value of a variable is less important than changes in value. In
these applications, only the irreducible errors (45 ppm = 0.004%)
are significant. Furthermore, if a system has an intelligent pro-
cessor monitoring the A-to-D output, the addition of a auto-
gain/autozero cycle will remove all reducible errors and may
eliminate the requirement for initial calibration. This will also
reduce errors to 0.004%.

+VS
+10V

10kV
350V 350V
RG1
14-BIT
G = 100 ADC
350V
AD524C 0V TO 2V
350V
F.S.
RG2

–VS

Figure 46. Typical Bridge Application

Table II. Error Budget Analysis of AD524CD in Bridge Application

Effect on Effect on
Absolute Absolute Effect
AD524C Accuracy Accuracy on
Error Source Specifications Calculation at TA = +25ⴗC at TA = +85ⴗC Resolution
Gain Error ± 0.25% ± 0.25% = 2500 ppm 2500 ppm 2500 ppm –
Gain Instability 25 ppm (25 ppm/°C)(60°C) = 1500 ppm – 1500 ppm –
Gain Nonlinearity ± 0.003% ± 0.003% = 30 ppm – – 30 ppm
Input Offset Voltage ± 50 µV, RTI ± 50 µV/20 mV = ± 2500 ppm 2500 ppm 2500 ppm –
Input Offset Voltage Drift ± 0.5 µV/°C (± 0.5 µV/°C)(60°C) = 30 µV
– 30 µV/20 mV = 1500 ppm – 1500 ppm –
Output Offset Voltage* ± 2.0 mV ± 2.0 mV/20 mV = 1000 ppm 1000 ppm 1000 ppm –
Output Offset Voltage Drift* ± 25 µV/°C (± 25 µV/°C)(60°C)= 1500 µV
1500 µV/20 mV = 750 ppm – 750 ppm –
Bias Current-Source ± 15 nA (± 15 nA)(100 Ω) = 1.5 µV
Imbalance Error 1.5 µV/20 mV = 75 ppm 75 ppm 75 ppm –
Bias Current-Source ± 100 pA/°C (± 100 pA/°C)(100 Ω)(60°C) = 0.6 µV
Imbalance Drift 0.6 µV/20 mV= 30 ppm – 30 ppm –
Offset Current-Source ± 10 nA (± 10 nA)(100 Ω) = 1 µV
Imbalance Error 1 µV/20 mV = 50 ppm 50 ppm 50 ppm –
Offset Current-Source ± 100 pA/°C (100 pA/°C)(100 Ω)(60°C) = 0.6 µV
Imbalance Drift 0.6 µV/20 mV = 30 ppm – 30 ppm –
Offset Current-Source ± 10 nA (10 nA)(175 Ω) = 3.5 µV
Resistance-Error 3.5 µV/20 mV = 87.5 ppm 87.5 ppm 87.5 ppm –
Offset Current-Source ± 100 pA/°C (100 pA/°C)(175 Ω)(60°C) = 1 µV
Resistance-Drift 1 µV/20 mV = 50 ppm – 50 ppm –
Common Mode Rejection 115 dB 115 dB = 1.8 ppm × 5 V = 8.8 µV
5 V dc 8.8 µV/20 mV = 444 ppm 444 ppm 444 ppm –
Noise, RTI
(0.1 Hz–10 Hz) 0.3 µV p-p 0.3 µV p-p/20 mV = 15 ppm – – 15 ppm
Total Error 6656.5 ppm 10516.5 ppm 45 ppm
*Output offset voltage and output offset voltage drift are given as RTI figures.

–14– REV. E
 AD524
Figure 47 shows a simple application, in which the variation of and the circuit near 25°C. If resistors with low tempcos are
the cold-junction voltage of a Type J thermocouple-iron(+)– used, compensation accuracy will be to within ± 0.5°C, for
constantan–is compensated for by a voltage developed in series temperatures between +15°C and +35°C. Other thermocouple
by the temperature-sensitive output current of an AD590 semi- types may be accommodated with the standard resistance values
conductor temperature sensor. shown in the table. For other ranges of ambient temperature,
the equation in the figure may be solved for the optimum values
RA
REFERENCE of RT and R A.
NOMINAL JUNCTION
TYPE VALUE +VS 7.5V
+158C < TA < +358C The microprocessor controlled data acquisition system shown in
J 52.3V
K 41.2V TA
IA 2.5V Figure 48 includes both autozero and autogain capability. By
AD580
E 61.4V
G = 100
dedicating two of the differential inputs, one to ground and one
T 40.2V VA AD590 to the A/D reference, the proper program calibration cycles can
+VS
S, R 5.76V
AD524 eliminate both initial accuracy errors and accuracy errors over
RA
IRON
EO
temperature. The autozero cycle, in this application, converts a
VT CONSTANTAN CU 52.3V number that appears to be ground and then writes that same
MEASURING 8.66kV
number (8-bit) to the AD7524, which eliminates the zero error
JUNCTION 52.3VIA + 2.5V –VS
EO = VT – VA +
52.3V
– 2.5V RT
OUTPUT
since its output has an inverted scale. The autogain cycle con-
1+
R 1kV AMPLIFIER verts the A/D reference and compares it with full scale. A multi-
≅ VT OR METER
plicative correction factor is then computed and applied to
NOMINAL VALUE
9135V subsequent readings.
Figure 47. Cold-Junction Compensation For a comprehensive study of instrumentation amplifier design
and applications, refer to the Instrumentation Amplifier Applica-
The circuit is calibrated by adjusting RT for proper output voltage tion Guide, available free from Analog Devices.
with the measuring junction at a known reference temperature

AD583 VREF
RG2

AD7507 AD524 VIN AD574A

AGND
RG1

–VREF
A0 A2 20kV
EN A1 20kV

10kV
AD7524
1/2
1/2 5kV AD712
AD712
LATCH DECODE

CONTROL MICRO-
PROCESSOR

ADDRESS
ADDRESS BUS BUS

Figure 48. Microprocessor Controlled Data Acquisition System

REV. E –15–
AD524
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).

16-Lead Ceramic DIP

(D-16)
0.005 (0.13) MIN 0.080 (2.03) MAX

C722e–0–4/99
16 9
0.310 (7.87)
0.220 (5.59)
1 8
0.320 (8.13)
PIN 1 0.290 (7.37)
0.840 (21.34) MAX 0.060 (1.52)
0.015 (0.38)
0.200 (5.08)
MAX 0.150
0.200 (5.08) (3.81)
0.125 (3.18) MAX
SEATING 0.015 (0.38)
0.023 (0.58) 0.100 0.070 (1.78)
(2.54) PLANE 0.008 (0.20)
0.014 (0.36) 0.030 (0.76)
BSC

20-Terminal Leadless Chip Carrier

(E-20A)
0.200 (5.08)
0.075 BSC
0.358 (9.09) 0.100 (2.54)
(1.91)
0.342 (8.69) 0.064 (1.63) REF 0.100 (2.54) BSC
SQ 0.015 (0.38)
0.095 (2.41) 19 3 MIN
0.075 (1.90) 18 20 4
0.358 0.028 (0.71)
1
TOP (9.09) 0.011 (0.28) 0.022 (0.56)
BOTTOM
VIEW MAX 0.007 (0.18) VIEW
SQ R TYP 0.050 (1.27)
14 8 BSC
0.075 (1.91)
13 9
REF
45° TYP
0.088 (2.24) 0.055 (1.40) 0.150 (3.81)
0.054 (1.37) 0.045 (1.14) BSC

16-Lead SOIC
(R-16)

0.4133 (10.50)
0.3977 (10.00)

16 9
0.4193 (10.65)
0.3937 (10.00)
0.2992 (7.60)
0.2914 (7.40)

1 8

PIN 1 0.1043 (2.65) 0.0291 (0.74)

x 45°
0.0118 (0.30) 0.0926 (2.35) 0.0098 (0.25)

PRINTED IN U.S.A.
0.0040 (0.10)

8° 0.0500 (1.27)
0.0500 0.0192 (0.49) 0° 0.0157 (0.40)
(1.27) SEATING 0.0125 (0.32)
0.0138 (0.35) PLANE
BSC 0.0091 (0.23)

–16– REV. E