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- VHDL khoâng phaân bieät chöõ vieát hoa vaø chöõ thöôøng.
databus Databus DataBus DATABUS
- VHDL laø ngoân ngöõ “ñònh daïng töï do”.
if (a=b) then
if (a=b) then
if (a =
b) then
NguyenTrongLuat 1
Thuaät ngöõ COMPONENT:
- Laø khaùi nieäm trung taâm moâ taû phaàn cöùng baèng VHDL ñeå bieåu
dieãn caùc caáp thieát keá töø coång ñôn giaûn ñeán 1 heä thoáng phöùc taïp.
nand2 mux2to1
d0
a
z d1 y
b
sel
NguyenTrongLuat 2
Maõ VHDL cô baûn
LIBRARY
khai baùo thö vieän
ENTITY
thöïc theå
ARCHITECTURE
kieán truùc
NguyenTrongLuat 3
Ví duï: Maõ VHDL moâ taû component NAND 2 ngoõ vaøo
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY nand_gate IS
PORT(
a a : IN STD_LOGIC;
z
b b : IN STD_LOGIC;
z : OUT STD_LOGIC);
END nand_gate;
NguyenTrongLuat 4
LIBRARY LIBRARY ieee;
USE ieee.std_logic_1164.all;
- LIBRARY: khai baùo thö vieän ieee
- USE: söû duïng caùc ñònh nghóa goùi (package) std_logic_1164
ENTITY Moâ taû caùc tín hieäu xuaát/nhaäp cuûa khoái component
ENTITY nand_gate IS
PORT(
a
z a : IN STD_LOGIC;
b b : IN STD_LOGIC;
z : OUT STD_LOGIC);
END nand_gate;
- ENTITY: ñaët teân cho entity (nand_gate)
- PORT: khai baùo caùc chaân xuaát/nhaäp
* Teân port (portname): a, b, z
* Kieåu port (mode): IN, OUT
* Kieåu tín hieäu (type): STD_LOGIC
NguyenTrongLuat 5
* Caùc kieåu chaân PORT I/0
IN: döõ lieäu ñi vaøo entity qua port vaø coù theå ñöôïc ñoïc trong entity.
OUT: döõ lieäu xuaát ra ngoaøi entity qua chaân port.
Port OUT khoâng theå ñoïc veà laïi entity.
INOUT: laø port 2 chieàu, cho pheùp döõ lieäu ñi vaøo hoaëc ra.
BUFFER: töông töï port OUT, nhöng ñöôïc pheùp ñoïc laïi bôûi entity.
IN OUT
BUFFER
IN INOUT
IN
OUT
NguyenTrongLuat 6
ARCHITECTURE
Moâ taû thieát keá beân trong cuûa khoái, chæ roõ moái quan heä
giöõa caùc ngoõ vaøo vaø ngoõ ra.
ARCHITECTURE model OF nand_gate IS
a BEGIN
z
b z <= a NAND b;
END model;
NguyenTrongLuat 7
ÑOÁI TÖÔÏNG DÖÕ LIEÄU (Data object)
* Tín hieäu (signal): bieåu dieãn cho caùc daây keát noái cuûa maïch.
Noù ñöôïc khai baùo trong phaàn PORT cuûa khai baùo entity hoaëc
trong phaàn ñaàu trong architecture (tröôùc BEGIN).
SIGNAL signal_name : signal_type;
SIGNAL a : std_logic;
* Bieán (Variable): ñöôïc khai baùo vaø söû duïng trong process.
Bieán khoâng phaûi laø tín hieäu logic thaät.
VARIABLE variable_name : variable_type;
VARIABLE b : std_logic;
* Haèng soá (Constant): giöõ moät giaù trò khoâng ñöôïc thay ñoåi
CONSTANT constant_name : constant_type;
CONSTANT max : integer;
Caùc ñoái töôïng döõ lieäu coù theå ñöôïc ñaët giaù trò ñaàu, khai baùo sau
phaàn khai baùo kieåu döõ lieäu _type:= value;
CONSTANT max : integer : = 25;
NguyenTrongLuat 8
* Söï khaùc nhau giöõa Tín hieäu (Signal) vaø Bieán (Variable)
- Pheùp gaùn bieán (Variable) cho giaù trò töùc thôøi, pheùp gaùn
cuûa tín hieäu (signal) bò treã (delay)
- Tín hieäu (Signal) coù theå quan saùt daïng soùng (waveform),
nhöng bieán (Variable) thì khoâng.
NguyenTrongLuat 9
KIEÅU DÖÕ LIEÄU (Data type)
- Caùc kieåu döõ lieäu laø ñaëc tính cuûa signal, variable, …
- Caùc döõ lieäu cuøng kieåu môùi ñöôïc gaùn hoaëc keát noái vôùi nhau
- Coù theå taïo ra caùc kieåu döõ lieäu môùi baèng leänh TYPE hoaëc
SUBTYPE
* Kieåu BIT vaø BIT_VECTOR:
- BIT coù giaù trò ‘0’ vaø ‘1’.
- BIT_VECTOR laø daõy (array) cuûa BIT.
* Kieåu INTEGER
* Kieåu BOOLEAN: coù giaù trò TRUE vaø FALSE.
* Kieåu CHARACTER
* Kieåu lieät keâ (ENUMERATION) do ngöôøi söû duïng ñònh nghóa.
* ...
NguyenTrongLuat 10
* STD_LOGIC: Value Meaning
‘X’ Forcing (Strong driven) Unknown
- Laø kieåu tín hieäu quyeát
‘0’ Forcing (Strong driven) 0
ñònh (coù theå ñöôïc laùi baèng
‘1’ Forcing (Strong driven) 1
2 ngoõ vaøo)
‘Z’ High Impedance
- Coù 9 giaù trò
‘W’ Weak (Weakly driven) Unknown
- Höõu ích khi moâ phoûng
Weak (Weakly driven) 0.
- Chæ coù 3 giaù trò ‘0’, ‘1’, ‘L’
Models a pull down.
‘Z’ laø coù theå toång hôïp Weak (Weakly driven) 1.
‘H’
Models a pull up.
‘-’ Don't Care
‘U’ Uninitialized
SIGNAL a: STD_LOGIC;
a laø tín hieäu STD_LOGIC kieåu 1 bit
SIGNAL b: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL c: STD_LOGIC_VECTOR(0 TO 7);
b,c laø tín hieäu STD_LOGIC kieåu bus coù 8 bit
NguyenTrongLuat 11
Pheùp gaùn tín hieäu kieåu STD_LOGIC
SIGNAL a: STD_LOGIC;
SIGNAL b: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL c: STD_LOGIC_VECTOR(0 TO 3);
SIGNAL d: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL e: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL f: STD_LOGIC_VECTOR(8 DOWNTO 0);
a <= ’1’; -- giaù trò gaùn ñaët giöõa 1 daáu nhaùy ñôn ‘ ’
a <= b(2); -- a <= b(2),
b <= "0000”; -- giaù trò gaùn ñaët giöõa 1 daáu nhaùy keùp “ ”
c <= B”0000”; -- B laø kyù hieäu cô soá 2 (coù theå boû)
d <= -- bieåu dieãn töøng nhoùm 4 bit phaân caùch _
”0110_0111”;
e <= X”AF67”; -- X laø kyù hieäu cô soá 16 (Hex)
f <= O”723”; -- O laø kyù hieäu cô soá 8 (Octal)
b <= c; -- b(3) <= c(0), b(2) <= c(1),
-- b(1) <= c(2), b(0) <= c(3)
d(7 downto 6)<= ”11”;
c(0 to 2)<= e(7 downto 5);
NguyenTrongLuat 12
Gheùp noái chuoãi (Concatenation)
SIGNAL a: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL b: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL c, d, e: STD_LOGIC_VECTOR(7 DOWNTO 0);
a <= ”0000”;
b <= ”1111”;
c <= a & b; -- c = “00001111”
e <= ’0’ & ’0’ & ’0’ & ’0’ & ’1’ & ’1’ &
’1’ & ’1’; -- e = “00001111”
NguyenTrongLuat 13
PHEÙP TOAÙN (Operator)
* Pheùp toaùn Logic (Logical Operator):
NOT AND OR NAND NOR XOR XNOR
Söû duïng cho kieåu: bit, bit_vector, boolean, std_logic, std_logic_vector.
* / MOD REM
NguyenTrongLuat 16
MOÂ TAÛ CAÁU TRUÙC (Structural description)
COMPONENT and2
x1
y PORT (x1,x2:IN STD_LOGIC;
x2 y: OUT STD_LOGIC);
END COMPONENT;
- Ñeå keát noái component caáp thaáp, thöïc hieän leänh thay theá trò
soá component (component instantiation) PORT MAP.
Coù 2 caùch: * Keát hôïp vò trí (positional association)
* Keát hôïp theo teân (named association)
NguyenTrongLuat 17
* Keát hôïp theo teân (named association)
COMPONENT component_name
port declarations;
END COMPONENT;
...
Label: component_name PORT MAP (
port_name1 => sig_name1,
port_name2 => sig_name2 );
COMPONENT and2
PORT (x1,x2:IN STD_LOGIC;
y: OUT STD_LOGIC);
END COMPONENT;
BEGIN
user1: and2 PORT MAP ( x1 => a, x2 => b,
y => c );
...
NguyenTrongLuat 18
* Keát hôïp vò trí (positional association)
COMPONENT component_name
port declarations;
END COMPONENT;
...
Label: component_name PORT MAP (
sig_name1, sig_name2, ... );
COMPONENT and2
PORT (x1,x2:IN STD_LOGIC;
y: OUT STD_LOGIC);
END COMPONENT;
BEGIN
user1: and2 PORT MAP ( a, b, c );
...
NguyenTrongLuat 19
a
VD: Thieát keá XOR 3 ngoõ vaøo u1_out
b
LIBRARY ieee; result
USE ieee.std_logic_1164.all; c
ENTITY xor3 IS
PORT ( a, b, c : IN STD_LOGIC;
result : OUT STD_LOGIC);
END xor3;
ARCHITECTURE structural OF xor3 IS
SIGNAL u1_out: STD_LOGIC;
COMPONENT xor2
PORT ( i1, i2 : IN STD_LOGIC;
y : OUT STD_LOGIC );
END COMPONENT;
BEGIN
u1: xor2 PORT MAP ( i1 => a, i2 => b,
y => u1_out);
u2: xor2 PORT MAP ( i1 => u1_out, i2 => c,
y => result);
END structural;
NguyenTrongLuat 20
MOÂ TAÛ LUOÀNG DÖÕ LIEÄU (Dataflow description)
- Moâ taû luoàng döõ lieäu di chuyeån töø ngoõ vaøo ñeán ngoõ ra.
- Caùc phaùt bieåu naøy ñöôïc thöïc thi cuøng thôøi ñieåm, vì vaäy thöù
töï caùc phaùt bieåu laø nhö nhau
NguyenTrongLuat 21
Pheùp gaùn baèng pheùp toaùn (OPERATOR)
a u1_out
b
result
c
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY xor3 IS
PORT ( a, b, c : IN STD_LOGIC;
result : OUT STD_LOGIC);
END xor3;
ARCHITECTURE dataflow OF xor3 IS
SIGNAL u1_out: STD_LOGIC;
BEGIN
u1_out <= a XOR b; Result <= u1_out XOR c;
Result <= u1_out XOR c; u1_out <= a XOR b;
END dataflow;
NguyenTrongLuat 22
Pheùp gaùn tín hieäu theo ñieàu kieän (Condition Signal Assigment)
WHEN - ELSE
signal_name <= value1 WHEN condition1 ELSE
{value2 WHEN condition2 ELSE}
valueN ;
LIBRARY ieee;
mux2to1
USE ieee.std_logic_1164.all;
d0 ENTITY mux2to1 IS
d1 y PORT ( d0, d1 : IN STD_LOGIC;
sel : IN STD_LOGIC;
sel y : OUT STD_LOGIC);
END mux2to1;
ARCHITECTURE dataflow2 OF mux2to1 IS
sel y BEGIN
0 d0 WITH sel SELECT
y <= d0 WHEN ’0’,
1 d1
d1 WHEN OTHERS;
END dataflow2;
NguyenTrongLuat 25
WITH select_signal SELECT
signal_name <= value1 WHEN const1_of_select_signal,
{value2 WHEN const2_of_select_signal,}
valueN WHEN OTHERS;
- Laø caáu truùc ñeå ñöa 1 haèng soá vaøo trong entity gioáng khai baùo
CONSTANT.
- Tieän lôïi cuûa generic laø coù theå söû duïng noù trong pheùp gaùn
thay theá trò soá töông ñöông component (component
instantitation), ñeå söû duïng caùc giaù trò haèng soá khaùc nhau khi
tham chieáu component.
ENTITY entity_name IS
GENERIC (
generic_name1: data_type := default_values;
generic_name2: data_type := default_values;
)
PORT (
port_name: mode data_type;
... )
END entity_name;
NguyenTrongLuat 29
* Khai baùo component coù GENERIC
COMPONENT component_name
GENERIC (
generic_name1: data_type := default_values;
...)
PORT (
port_name: mode data_type;
...)
END COMPONENT;
NguyenTrongLuat 30
MOÂ TAÛ HAØNH VI ( Behavioral description)
- Moâ taû söï ñaùp öùng cuûa ngoõ ra theo ngoõ vaøo.
- Söû duïng phaùt bieåu PROCESS chöùa caùc leänh ñöôïc thöïc thi
tuaàn töï, phuï thuoäc vaøo thöù töï cuûa noù
- Caùc phaùt bieåu tuaàn töï (Sequential statement): cho pheùp moâ taû
hoaït ñoäng tuaàn töï cuûa caùc tín hieäu
* Phaùt bieåu IF
* Phaùt bieåu CASE
* Phaùt bieåu LOOP
NguyenTrongLuat 31
PROCESS
- Process thöïc hieän caùc leänh beân trong noù 1 caùch tuaàn töï.
Vì vaäy thöù töï cuûa caùc leänh raát quan troïng.
- Process ñöôïc kích hoaït khi coù söï thay ñoåi cuûa 1 tín hieäu.
NguyenTrongLuat 33
Phaùt bieåu IF - THEN - ELSE
IF condition1 THEN sequential_statements_1;
{ELSIF condition2 THEN sequential_statements_1;}
{ELSE sequential_statements_1;}
END IF;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
VD: Mux2to1 ENTITY mux2to1 IS
mux2to1 PORT ( d0, d1 , sel : IN STD_LOGIC;
d0 y : OUT STD_LOGIC);
END mux2to1;
d1 y ARCHITECTURE behavior1 OF mux2to1 IS
sel BEGIN
PROCESS (d0, d1, sel)
BEGIN
IF sel = ’0’ THEN y <= d0 ;
sel y ELSE y <= d1 ;
0 d0 END IF;
1 d1 END PROCESS;
END behavior1;
NguyenTrongLuat 34
Phaùt bieåu CASE - WHEN
CASE select_signal IS
WHEN value1 => sequential_statements_1;
WHEN value2 => sequential_statements_2;
WHEN OTHERS => sequential_statements_N;
END CASE;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
VD: Mux2to1 ENTITY mux2to1 IS
mux2to1 PORT ( d0, d1 , sel : IN STD_LOGIC;
y : OUT STD_LOGIC);
d0 END mux2to1;
d1 y ARCHITECTURE behavior2 OF mux2to1 IS
BEGIN
sel PROCESS (d0, d1, sel)
BEGIN
CASE sel IS
sel y WHEN ’0’ => y <= d0 ;
WHEN OTHERS => y <= d1 ;
0 d0 END CASE;
1 d1 END PROCESS;
END behavior2;
NguyenTrongLuat 35
Phaùt bieåu FOR - LOOP
NguyenTrongLuat 36
Phaùt bieåu WHILE - LOOP
i:=0;
WHILE (i<10) LOOP
s <= i;
i := i+1;
END LOOP;
NguyenTrongLuat 37
THIEÁT KEÁ HEÄ TOÅ HÔÏP BAÈNG VHDL
- Heä toå hôïp coù theå ñöôïc thöïc hieän baèng caùc phaùt bieåu ñoàng
thôøi (concurent statement) vaø tuaàn töï (sequential statement).
- Phaùt bieåu tuaàn töï (sequent statement) ñöôïc duøng trong moâ taû
haønh vi (dataflow description)
NguyenTrongLuat 38
fulladder
BOÄ COÄNG
x
y
s s=x⊕ y⊕ z A
c D
z c=xy +yz +xz D
E
R
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fulladder IS
PORT ( x , y , z : IN STD_LOGIC;
s , c : OUT STD_LOGIC);
END fulladder;
NguyenTrongLuat 39
adder4
- Heä tuaàn töï chæ ñöôïc thöïc hieän baèng caùc phaùt bieåu tuaàn töï
(sequential statement).
- Thöïc hieän: maïch choát, FF, thanh ghi, boä ñeám, maùy traïng
thaùi.
- Bieán (Variable) chæ toàn taïi cuïc boä trong Process, vì vaäy muoán
laáy giaù trò cuûa bieán ra ngoaøi Process thì ta phaûi gaùn bieán cho
tín hieäu (Signal).
- Trong Process, bieán ñöôïc caäp nhaät giaù trò sau moãi phaùt bieåu;
coøn tín hieäu chæ ñöôïc caäp nhaät ôû cuoái Process.
NguyenTrongLuat 53
MAÏCH CHOÁT
Dlatch
LIBRARY ieee;
D Q USE ieee.std_logic_1164.all;
ENTITY Dlatch IS
PORT (D, Clk : IN STD_LOGIC;
Q, Qn : OUT STD_LOGIC);
Clk Q END Dlatch;
ARCHITECTURE behavior OF Dlatch IS
BEGIN
PROCESS (D, Clk)
clk D Q+ Q+ BEGIN
0 X Q Q IF Clk = ’1’ THEN
1 0 0 1 Q <= D;
1 1 1 0 Qn <= NOT Q;
END IF;
END PROCESS;
END behavior;
NguyenTrongLuat 54
LIBRARY ieee;
FLIP - FLOP
USE ieee.std_logic_1164.all; Dflipflop
ENTITY Dflipflop IS
PORT (D, Clk : IN STD_LOGIC; D Q
Q, Qn : OUT STD_LOGIC);
END Dflipflop;
ARCHITECTURE behavior OF Dflipflop IS
BEGIN clk Q
PROCESS (Clk)
BEGIN
IF Clk’event AND Clk = ’1’ THEN
Q <= D; IF rising_edge(clk) THEN
Qn <= NOT Q;
END IF;
END PROCESS;
END behavior;
- clk’event phaùt hieän söï thay ñoåi tín hieäu clk töø 0 leân 1 hoaëc töø 1 veà 0.
- Goùi std_logic_1164 coù ñònh nghóa 2 haøm (function): rising_edge ñeå phaùt
hieän caïnh leân vaø falling_edge ñeå phaùt hieän caïnh xuoáng cuûa tín hieäu.
NguyenTrongLuat 55
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY DFF IS
PORT (D, Clk, Pr, Cl : IN STD_LOGIC;
Q, Qn : OUT STD_LOGIC);
Pr END DFF;
ARCHITECTURE behavior OF DFF IS
D Q
BEGIN
DFF PROCESS (Clk, Pr, Cl)
BEGIN
Clk Q IF Pr = ’0’ THEN Q <= ’1’;
Cl Qn <= ’0’;
ELSIF Cl = ’0’ THEN Q <= ’0’;
Qn <= ’1’;
ELSIF Clk’event AND Clk = ’0’ THEN
Q <= D;
Qn <= NOT Q;
END IF;
END PROCESS;
END behavior;
NguyenTrongLuat 56
Thanh ghi (register)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY regn IS
GENRERIC (n : NATURAL := 4);
PORT (D : IN STD_LOGIC_VECTOR(n-1 downto 0);
Clk, Reset : _VECTORIN STD_LOGIC;
Q : OUT STD_LOGIC(n-1 downto 0));
END regn; n n
ARCHITECTURE behavioral OF regn IS D Q
BEGIN
PROCESS (Clk, Reset, D)
regn
BEGIN Clk
IF (Reset = '0') THEN
Reset
Q <= (others => '0');
ELSIF rising_edge(Clock) THEN
Q <= D;
END IF; GENRERIC (n : NATURAL := 4)
END PROCESS; Khai baùo generic n laø natural (soá nguyeân döông)
END behavioral; Q <= (Others=> ‘0’) töông ñöông vôùi Q <= “0000”
NguyenTrongLuat 57
BOÄ ÑEÁM LEÂN 4 BIT
coù Reset baát ñoàng boä BOÄ ÑEÁM (COUNTER)
LIBRARY ieee; Upcnt4
USE ieee.std_logic_1164.all
USE ieee.std_logic_unsigned.all;
Rst Q0
ENTITY Upcnt4 IS
PORT (Clk, Rst : IN STD_LOGIC; Q1
Q: OUT STD_LOGIC_VECTOR(3 downto 0)); Q2
END Upcnt4; Clk Q3
ARCHITECTURE Behavioral OF Upcnt4 IS
BEGIN
PROCESS (Clk, Rst)
VARIABLE count: STD_LOGIC_VECTOR (3 downto 0);
BEGIN
IF Rst ='1' THEN
count := (others=>'0');
ELSIF rising_edge(clk) THEN
count := count + "0001";
END IF; Söû duïng bieán count ñeå thöïc hieän chöùc naêng boä ñeám
Q <= count;
END PROCESS; Bieán count ñöôïc gaùn cho ngoõ ra Q ôû cuoái Process,
END Behavioral; vì bieán laø giaù trò cuïc boä trong Process
NguyenTrongLuat 58
LIBRARY ieee;
USE ieee.std_logic_1164.all
USE ieee.std_logic_unsigned.all;
ENTITY Upcnt4 IS
PORT ( Clk, Rst : IN STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR(3 downto 0));
END Upcnt4;
ARCHITECTURE Behavioral OF Upcnt4 IS
SIGNAL count: STD_LOGIC_VECTOR (3 downto 0);
BEGIN
PROCESS (Clk, Rst)
Boä ñeám BEGIN
coù reset IF rising_edge(clk) THEN
ñoàng boä IF Rst ='1' THEN
count <= (others=>'0');
ELSE
count <= count + "0001";
END IF;
END IF;
END PROCESS; Söû duïng tín hieäu count thay cho bieán count.
Q <= count;
Tín hieäu count ñöôïc gaùn cho ngoõ ra Q beân
END Behavioral;
ngoaøi Process.
NguyenTrongLuat 59
LIBRARY ieee;
USE ieee.std_logic_1164.all BOÄ ÑEÁM LEÂN
USE ieee.std_logic_unsigned.all; THAÄP PHAÂN
ENTITY Upcnt10 IS
PORT ( Clk, Rst : IN STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR(3 downto 0));
END Upcnt10;
ARCHITECTURE Behavioral OF Upcnt10 IS
BEGIN
PROCESS (Clk, Rst)
VARIABLE count: STD_LOGIC_VECTOR (3 downto 0);
BEGIN
IF Rst ='1' THEN
count := (others=>'0');
ELSIF rising_edge(clk) THEN
IF count = "1001" then
count := (others=>'0');
ELSE count := count + "0001";
END IF;
END IF;
Q <= count;
END PROCESS;
END Behavioral;
NguyenTrongLuat 60
LIBRARY ieee;
USE ieee.std_logic_1164.all BOÄ ÑEÁM 4 bit
USE ieee.std_logic_unsigned.all; LEÂN / XUOÁNG
ENTITY Updncnt4 IS
PORT ( Clk, Rst, Updn: IN STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR(3 downto 0));
END Updncnt4;
ARCHITECTURE Behavioral OF Updncnt4 IS
SIGNAL count: STD_LOGIC_VECTOR (3 downto 0);
BEGIN
PROCESS (Clk, Rst)
BEGIN
IF Rst = ’1’ THEN
count <= (others =>’0’); Updn Q0
ELSIF rising_edge(Clk) THEN Q1
IF Updn = ’1’ THEN Rst Q2
count <= count + ”0001”;
Clk Q3
ELSE count <= count - ”0001”;
END IF; Updncnt4
END IF;
END PROCESS;
Q <= count;
END Behavioral;
NguyenTrongLuat 61
Thanh ghi dòch (shift reg.)
LIBRARY ieee;
USE ieee.std_logic_1164.all; n S
ENTITY sipo IS
Serin Q I
GENERIC (n: NATURAL := 8); sipo P
PORT (Serin, Clk : IN STD_LOGIC;
Clk
O
Q : OUT STD_LOGIC_VECTOR(
n-1 downto 0));
END sipo;
ARCHITECTURE shiftreg OF sipo IS
SIGNAL reg : STD_LOGIC_VECTOR(n-1 downto 0);
BEGIN
PROCESS (Clk)
BEGIN
IF rising_edge(Clk) THEN
reg <= reg(n-2 downto 0) & Serin;
END IF;
END PROCESS;
Q <= reg;
END shiftreg;
NguyenTrongLuat 62
S
I
S siso
O LIBRARY ieee;
Serin
USE ieee.std_logic_1164.all;
ENTITY siso IS
GENERIC (n : NATURAL := 8); Serout
PORT (Clk, Serin : IN STD_LOGIC;
Serout : OUT STD_LOGIC); Clk
END siso;
ARCHITECTURE shiftreg OF siso IS
SIGNAL reg : STD_LOGIC_VECTOR(n-1 downto 0);
BEGIN
PROCESS (Clk)
BEGIN
IF rising_edge(Clk) THEN
reg <= reg(n-2 downto 0) & Serin;
END IF;
END PROCESS;
Serout <= reg(n-1);
END shiftreg;
NguyenTrongLuat 63
piso
LIBRARY ieee; Clk
USE ieee.std_logic_1164.all; ShLd
ENTITY piso IS Serin
GENERIC (n: NATURAL := 8); n
PORT (Serin, Clk, ShLd : IN STD_LOGIC; D Serout
D : IN STD_LOGIC_VECTOR(n-1 downto 0);
Serout : OUT STD_LOGIC);
END piso;
ARCHITECTURE shiftreg OF piso IS
SIGNAL reg : STD_LOGIC_VECTOR(n-1 downto 0);
BEGIN
PROCESS (Clk)
BEGIN
IF rising_edge(Clk) THEN
IF ShLd = ’0’ THEN
reg <= D;
ELSE reg <= reg(n-2 downto 0) & Serin; P
END IF; I
END PROCESS;
Serout <= reg(n-1);
S
END shiftreg; O
NguyenTrongLuat 64
MAÙY TRAÏNG THAÙI
FSM
- Maùy traïng thaùi höõu haïn ñöôïc thieát keá deã daøng baèng phaùt
bieåu PROCESS.
- Vieäc chuyeån traïng thaùi ñöôïc moâ taû trong Process vôùi danh
saùch caûm nhaän (sensitivity list) laø clock vaø tín hieäu reset baát
ñoàng boä.
- Ngoõ ra coù theå ñöôïc moâ taû baèng caùc phaùt bieåu ñoàng thôøi
(concurrenrt) naèm ngoaøi process.
- Coù 2 kieåu FSM: MOORE vaø MEALY
NguyenTrongLuat 65
Inputs Next State
MOORE
function FSM
Next State Present State
clock Present State
reset Register
Output Outputs
function
Present State Register: thanh ghi traïng thaùi hieän taïi löu giöõ 1
traïng thaùi hieän taïi, seõ chuyeån traïng thaùi khi coù xung clock.
Next state function: haøm traïng thaùi keá tieáp laø maïch toå hôïp phuï
thuoäc vaøo ngoõ vaøo vaø traïng thaùi hieän taïi
Output function: haøm ngoõ ra laø maïch toå hôïp phuï thuoäc vaøo traïng
thaùi hieän taïi
NguyenTrongLuat 66
FSM kieåu MOORE ñöôïc moâ taû baèng 3 PROCESS
- Process Haøm ngoõ ra coù theå thay theá baèng caùc phaùt bieåu
ñoàng thôøi (concurrent statement)
- Process 2 vaø 3 coù theå keát hôïp thaønh 1 Process.
NguyenTrongLuat 67
LIBRARY ieee; Process Thanh ghi traïng thaùi:
USE iee.std_logic_1164.all; PROCESS (reset, clock)
ENTITY Moore_FSM IS
PORT (clock, rerset, input: IN std_logic;
output: OUT std_logic);
END Moore_FSM;
ARCHITECTURE behavior OF Moore_FSM IS
TYPE state IS (list of states);
SIGNAL pr_state, nx_state: state;
BEGIN
PROCESS(clk, reset)
BEGIN
IF reset = ’1’ THEN
pr_state <= reset state;
ELSIF (clock = ’1’ and clock’event) THEN
pr_state <= nx_state;
END IF;
END PROCESS;
TYPE state IS (list of states): khai baùo state laø döõ lieäu kieåu lieät keâ
NguyenTrongLuat 68
Process Haøm traïng thaùi keá tieáp:
PROCESS (input, present_state)
PROCESS (input, ps_state )
CASE ps_state IS
WHEN state_1 =>
IF input = ’…’ THEN
nx_state <= state_2;
ELSIF nx_state <= state_3;
END IF;
WHEN state_2 =>
IF input = ’…’ THEN
nx_state <= state_1;
ELSIF nx_state <= state_3;
END IF;
. . .
END CASE;
END PROCESS;
NguyenTrongLuat 69
Process Haøm ngoõ ra:
PROCESS (present_state)
PROCESS(ps_state )
CASE ps_state IS
WHEN state_1 =>
output <= ’...’;
WHEN state_2 =>
output <= ’...’;
...
END CASE;
END PROCESS;
Coù theå thay theá process naøy baèng phaùt bieåu ñoàng thôøi
output <= ... ;
NguyenTrongLuat 70
TT TT keá tieáp Ngoõ ra
hieän taïi x = 0 x = 1 (z)
S0 S0 S1 0
LIBRARY ieee;
S1 S2 S1 0
USE iee.std_logic_1164.all;
ENTITY Moore_FSM IS S2 S0 S3 0
PORT ( S3 S2 S1 1
clock, rerset, x: IN std_logic;
z: OUT std_logic);
END Moore_FSM;
ARCHITECTURE behavior OF Moore_FSM IS
TYPE state IS (S0, S1, S2, S3);
SIGNAL pr_state, nx_state: state;
BEGIN
regst: PROCESS(clk, reset)
BEGIN
IF reset = ’1’ THEN pr_state <= S0;
ELSIF (clock = ’1’ and clock’event) THEN
pr_state <= nx_state;
END IF;
END PROCESS;
NguyenTrongLuat 71
TT TT keá tieáp Ngoõ ra
nxst: PROCESS (x, ps_state )
hieän taïi x = 0 x = 1 (z)
CASE ps_state IS
WHEN S0 =>
S0 S0 S1 0
IF x = ’0’ THEN
S1 S2 S1 0
nx_state <= S0;
S2 S0 S3 0
ELSIF nx_state <= S1;
S3 S2 S1 1
END IF;
WHEN S1 =>
IF x = ’0’ THEN nx_state <= S2;
ELSIF nx_state <= S1;
END IF;
WHEN S2 =>
IF x = ’0’ THEN nx_state <= S0;
ELSIF nx_state <= S3;
END IF;
WHEN S3 =>
IF x = ’0’ THEN nx_state <= S2;
ELSIF nx_state <= S1;
END IF;
END CASE;
END PROCESS;
NguyenTrongLuat 72
TT TT keá tieáp Ngoõ ra
hieän taïi x = 0 x = 1 (z)
Output: PROCESS(ps_state )
CASE ps_state IS S0 S0 S1 0
WHEN S3 => S1 S2 S1 0
z <= ’1’; S2 S0 S3 0
S3 S2 S1 1
WHEN OTHERS =>
z <= ’0’;
END CASE;
END PROCESS;
END behavior;
Output: PROCESS(ps_state )
IF ps_state = S3 THEN z <= ’1’;
ELSE ’0’;
END IF;
NguyenTrongLuat 73
nx_out: PROCESS (x, ps_state ) TT TT keá tieáp Ngoõ ra
CASE ps_state IS hieän taïi x = 0 x = 1 (z)
WHEN S0 =>
z <= ’0’; S0 S0 S1 0
IF x = ’0’ THEN S1 S2 S1 0
nx_state <= S0; S2 S0 S3 0
ELSIF nx_state <= S1; S3 S2 S1 1
END IF;
WHEN S1 =>
z <= ’0’;
IF x = ’0’ THEN nx_state <= S2;
ELSIF nx_state <= S1; END IF;
WHEN S2 =>
z <= ’0’;
IF x = ’0’ THEN nx_state <= S0;
ELSIF nx_state <= S3; END IF;
WHEN S3 =>
z <= ’1’;
IF x = ’0’ THEN nx_state <= S2;
ELSIF nx_state <= S1; END IF;
END CASE;
END PROCESS;
END behavior; Keát hôïp Process 2 vaø 3 thaønh 1 Process
NguyenTrongLuat 74
MEALY
FSM
FSM kieåu MEALY ñöôïc moâ taû baèng 2 PROCESS
Output Outputs
function
NguyenTrongLuat 75
Process Haøm traïng thaùi keá tieáp vaø Ngoõ ra:
PROCESS (input, present_state)
NguyenTrongLuat 76
nx_out: PROCESS (x, ps_state ) TT TT keá tieáp Ngoõ ra (Z)
CASE ps_state IS HT X = 0 1 X = 0 1
WHEN S0 =>
IF x = ’0’ THEN S0 S0 S1 0 0
z <= ’0’;
nx_state <= S0; S1 S2 S1 0 0
ELSIF S2 S2 S1 0 1
z <= ’0’;
nx_state <= S1;
END IF;
WHEN S1 =>
IF x = ’0’ THEN
z <= ’0’;
nx_state <= S2;
ELSIF
z <= ’0’;
nx_state <= S1;
END IF;
WHEN S2 =>
IF x = ’0’ THEN
z <= ’0’;
nx_state <= S2;
ELSIF
z <= ’0’;
nx_state <= S1;
END IF;
END CASE;
END PROCESS;
NguyenTrongLuat 77
Gán trạng thái
- Vieäc gaùn traïng thaùi thöôøng laø töï ñoäng.
TYPE state IS (S0, S1, S2);
SIGNAL pr_state, nx_state: state;
- Ta coù 2 caùch ñeå gaùn cho moãi traïng thaùi baèng 1 toå hôïp nhò phaân:
* Khai baùo constant
TYPE state IS STD_LOGIC_VECTOR(1 downto 0);
CONSTANT S0: state:= ”00”;
CONSTANT S1: state:= ”01”;
CONSTANT S2: state:= ”11”;
SIGNAL pr_state, nx_state: state;