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if(pwm_flag_h == 0)
temp_h = count_h;
executes only once inside the else block ( i.e when pwm_in == 0 ). In the next iteration of the always block
when the pwm_in is zero the above statement wont execute since the pwm_flag_h was set to high. Hence the
negedge of the pwm_in signal has been detected.
The same algorithm applies for the posedge detection inside the negative level detection block.
In both the blocks the total count value for the positive level and negative level has been assigned to the temp_h
and temp_l at negedge and posedge of the pwm_in.
Finally the temp_h and temp_l values are assigned to the output ports of the module at the end of the pwm_in
pulse ( i.e at negedge ).
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Full Verilog Code for PWM:-
module pwm_detect( input clk,
input pwm_in,
output reg [0:31] high_count,
output reg [0:31] low_count
);
endmodule
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