Simulation of PIR Based Security Alert System

using VHDL
Ramirez, Barry A.1, Paciolco, Aura Clarice J.1, Dela Peña,Darlene Joy A.1,Dantes, Judy Ann V. 1, Engr. Rionel B. Caldo2
Department of Computer Engineering

Tanauan City College

Brgy. Trapiche, Tanauan City, Batangas, 4232, Philippines

1
Abstract— In this paper, the match in masking
PIR based alert system is conditions is
carried out through the use of detected upon
VHDL to test the effectivity of
evaluation.
the program through
simulations. The system is
responsible to send an
indication through signals if 2. METHODOLOGY
the security of an area is being
breached. The signal will be
generated when a match in 2.1 VHDL Programming
masking conditions is present. Language

Keywords— Xilinx, Verilog VHDL is a programming

HDL, PIR, anti-masking language used in electronic
evaluation, signals automation to explain digital
and mixed-signal systems
1. INTRODUCTION such as field-programmable
As the rate of crimes in the gate arrays and integrated
country is said to be circuits.
increasing the need for a
security system must be a
priority nowadays. However, 2.2 Block Diagram
simulations of such product
must be presented first in
order to test the integrity of
the system it offers. The use
of masking conditions is
essential to demonstrate its
difference with normal
condition, a match of a
masking condition in the
simulation will generate an
alarm signal to the system.

1.1 Objectives of the

Study
The main objective of this
paper is to use VHDL as the
main controller of the system
while performing
simulations.
Specifically, this study aims
to present the following:
The sensor signal serves
as the input of the system, it
will be then processed by the
use of VHDL. The program
includes an anti-masking
evaluation. This masking
evaluation serve to identify
whether the captured signal is
a normal condition or
masking condition.

 To initiate an anti- 2.3 Flowchart

masking evaluation
upon detection of
certain conditions
using signals.
 To test the
effectivity of the
program through
simulations.
 To generate an
alarm signal when a

2
 2.4 PSEUDOCODE normal conditions. This will 11 1 0 1 1 1
be processed through the use 12 1 1 0 0 1
1. Start of an anti-masking 13 1 1 0 1 1
2. Initialization of evaluation. Through this, we 14 1 1 1 0 1
sensor signal will be informed that whether 15 1 1 1 1 1
3. If PIR is equal to 1 the host area detected some
it will proceed, if No movement. This is
it will initialize implemented through the use
again the sensor of signals.
signal. Simulation Results
4. The system will 3.2 Properties of the Project
process an anti- The system used the
masking evaluation. Verilog HDL to implement
5. GSM will give a the proposed project. This
signal. language provides different
6. Message will be kinds of simulations in order Fig.2 Low level block of PIR Based
Security Alert System
displayed to give a desired outputs.
7. Capture signal
continually create a 3.3 Functions of the System
signal to be
displayed in the The system The above figures
output. simulation can detect a shows the RTL schematics of
8. End. normal condition or masking the program. The inputs and
condition using a sensor outputs are clearly seen on
2.5 IPO CHART signal. .A match to the those figures. Inside those
masking condition will RTL was the logical
TABLE 1 triggered the alert to occur. operations processed by the
IPO Chart This will be seen to the system. These figures will
Input Processprogram through signals. The help you to identify the flow
-PIR signal - System receive the
system will also then of the program if you know
input coming how to read based on logical
continually
from the sensor capturing the
signalsit in order to provide a
and process operations.
using displayed outputs.
conditional
3.4 Tools and Methodologies
statement
(Maskingof the System
condition).
- Transfer the
information
through
different
signals

TABLE 2. Truth Table

3. RESULTS AND
DISCUSSIONS Inputs (Sensor Signal)
W X Y Z Cam_sig
3.1 Project Description 0 0 0 0 0 0
1 0 0 0 1 0
The system is 2 0 0 1 0 0
capable of sensing a motion 3 0 0 1 1 0
through the use of sensors. 4 0 1 0 0 0
This project shows that the 5 0 1 0 1 0
researcher will implement the
6 0 1 1 0 0
processed of security alert
7 0 1 1 1 0
system through simulations.
8 1 0 0 0 1
It is capable to identify Fig.1 Top level block of PIR Based
whether the PIR detected a 9 1 0 0 1 1
Security Alert System
10 1 0 1 0 1

3
 5. ACKNOWLEDGEMEN [2]
TS [ONLINE].AVAILABLE:HTT
First and foremost P://PEOPLE.ECE.CORNELL.
we have to thank God for EDU./VERILOG/.HTML/
giving us strength and [ACCESSED:APRIL 10,
wisdom to make this happen 2019].
because without Him we
[3] [ONLINE].
Fig.3 Simulations Results of all the were not able to accomplish
cases of masking condition AVAILABLE: HTTP://WWW.
this, specially our Advanced
REASEARCHGATE.NET
Logic Circuits professor
This simulations [ACCESSED:APRIL 11,
Engr. Rionel B. Caldo for his
shows the test benches of the 2019].
undying support, for teaching
program. It is the working us all the things we have to [4] [ONLINE].
process that show different learn about this course, AVAILABLE:
situations of the system. We teaching style and HTTP://WWW.PANTECHSOL
will see that it performs enthusiasm that made us UTIONS.NET/FPGA.HTML
clearly an antimasking believe that we can pass after ACCESSED:APRIL 11,
evaluation. all the hardships we've been 2015].
through. He always wanted
us to gain more knowledge
4. CONCLUSIONS from him after meet up with
him. We are so blessed to
We concluded that have him as a professor in
Verilog HDL is very flexible 7. APPENDICES
this course. We would like to
in doing any project thank him very much for the
simulations. It is user support and understanding, 7.1 Verilog Code
friendly and very easy to use. for his assistance and
In order for us to learn the dedicated involvement `timescale 1us / 10ns
algorithm of this is to read throughout the process. ///////////////////////////////////////
and study more about VHDL. We also want to ///////////////////////////////////////////
We also concluded that the show our sincerest gratitude // Company: TANAUAN
program we build is very to our close friends who CITY COLLEGE
easy. As it only used a short opened his home when we // Team Name: Team EPIC
code. But this paper clearly are in need of resources. We //
explains the processed of PIR have many persons to thank // Create Date: 09:49:46
based Security Alert System. for the help they had given to 04/10/2019
us. Most importantly my // Module Name:
groupmates (Team Epic) security_PIR
because this // Project Name: PIR
paper/documentation requires Based Security Alert System
a lot of academic support, we // Target Devices: PIR
all have a contribution on Based Security Alert System
doing this paper, we exert a Simulation
lot of time and effort. After ///////////////////////////////////////
all the stresses we ///////////////////////////////////////////
encountered we still had time
to rejoice doing this. module
security_PIR(PIR_sensor,W,
Y,Z,camera_signal,GSM_sig
6. REFERENCES nal,alarm_signal);
input PIR_sensor;
[1] [ONLINE]. input Y;
AVAILABLE: input W;
HTTP://WWW.ASIC- input Z;
WORLD.COM/VERILOG.HT output
ML/[ACCESSED:APRIL 10, camera_signal;
2019]. output GSM_signal;

4
 output alarm_signal; 7.2 TestBenches .
reg GSM_signal; W(W),
reg alarm_signal; `timescale 1us / .Y
10ns (Y),
.Z
assign camera_signal = ////////////////////////// (Z),
PIR_sensor; ////////////////////////////// .ca
always @(PIR_sensor or ///////////////// mera_signal(camera
alarm_signal or // Company: _signal),
GSM_signal ) TANAUAN CITY .G
if COLLEGE SM_signal(GSM_si
(PIR_sensor>=1) // Team Name: gnal),
begin TEAM EPIC .al
// arm_signal(alarm_si
alarm_signal = 1; // Create Date: gnal)
23:01:40 04/13/2019 );
GSM_signal = 1; // Design Name: initial
security_PIR begin
// Module Name: //
$display("Movement C:/Users/Documents case1
Detected"); /eagle/PIR_tb.v
end // Project Name: PIR_sensor
PIR Security Alert =0;
endmodule System Simulation W
// Target Device: = 0;
PIR Security Alert Y
System Simulation = 0;
Testbench Z
////////////////////////// = 0;
//////////////////////////////
/////////////////
#1;
module PIR_tb; // case2
PIR_sensor =0;
// Inputs W
reg = 0;
PIR_sensor; Y
reg W; = 0;
reg Y; Z
reg Z; = 1;

// Outputs
wire #1;
camera_signal; //
wire case3
GSM_signal;
wire PIR_sensor
alarm_signal; =0;
W
// = 0;
Instantiate the Unit Y
Under Test (UUT) = 1;
Z
security_PIR dut ( = 0;
.PI
R_sensor(PIR_senso
r),

5
 Z Y
#1; = 0; = 1;
// Z
case4 #1; = 0;
//
PIR_sensor case8 #1;
=0; //
W PIR_sensor case12 #1;
= 0; =0; //
Y W PIR_sensor case16
= 1; = 1; =1;
Z Y W PIR_sensor
= 1; = 1; = 0; =1;
Z Y W
= 1; = 1; = 1;
Z Y
#1; = 1; = 1;
// Z
case5 #1; = 1;
// #1;
PIR_sensor case9 //
=0; case13
W PIR_sensor #1;
= 1; =1; PIR_sensor
Y W =1;
= 0; = 0; W end
Z Y = 1;
= 0; = 0; Y endmodule
Z = 0;
= 0; Z
#1; = 0;
//
case6
#1; #1;
PIR_sensor // //
=0; case10 case14
W
= 1; PIR_sensor PIR_sensor
Y =1; =1;
= 0; W W
Z = 0; = 1;
= 1; Y Y
= 0; = 0;
Z Z
= 1; = 1;
#1;
//
case7 #1;
// #1;
PIR_sensor case11 //
=0; case15
W PIR_sensor
= 1; =1; PIR_sensor
Y W =1;
= 1; = 0; W
Z Y = 1;
= 0; = 1;