Pipelining

By K. Santle Camilus Based on the Text Book Computer Organization by Carl Hamacher et al., Fifth Edition

Introduction to Pipelining
Laundry Example Ann, Brian, Cathy, Dave each have one load of clothes to wash, dry, and fold Washer takes 30 minutes
Dryer takes 40 minutes Folder takes 20 minutes

Sequential Laundry
6 PM 7 8 9
Time

10

11

Midnight

30 40 20 30 40 20 30 40 20 30 40 20
T a s k O r d e r

A B C D

Sequential laundry takes 6 hours for 4 loads If they learned pipelining, how long would laundry take?

Pipelined Laundry Start work ASAP

6 PM 7 8 9
Time

10

11

Midnight

30 40
T a s k O r d e r

40

40

40 20

A B

C
D Pipelined laundry takes 3.5 hours for 4 loads Speedup = 6/3.5 = 1.7

Pipelining Lessons
6 PM
T a s k O r d e r

9
Time

30 40 A B C D

40

40

40 20

Pipelining doesnt help latency of single task, it helps throughput of entire workload Pipeline rate limited by slowest pipeline stage Multiple tasks operating simultaneously Potential speedup = Number pipe stages ??? Unbalanced lengths of pipe stages reduces speedup

Computer Pipelines
Pipelining: An implementation technique that overlaps the execution of multiple instructions. Execute billions of instructions, so throughput is what matters

Claim: (1) In pipelined two stage of execution, rate of instruction execution is twice than that achievable by sequential operation. In four stage, it is four times. (2) Increase in performance is directly propositional to the number of pipeline stages

Hardware Organization for Four Stage Pipelining

Time for execution

If different stages require different amount of time, the clock period must allow the longest stage to complete. ------ can we come up with a equation for this????? ------- using this, can we generalize the time taken for sequential and pipeline execution????? Pipelining does not result in individual instructions being executed faster; rather the throughput that increases

No cache in a computer. What happens to pipelining?

Perhaps it is related to time issue. Hamacher says: Accessing a main memory is 10 times greater than the time to execute a basic operation inside a processor If so, what happens to Pipelining ? Pipelining is more effective if different stage requires same amount of time.

Now the role of cache?

Hazards

Any condition that causes the pipeline to stall (key term meaning delay) is called a Hazard.

Types:

Data Hazard Control or instruction Hazard Structural Hazard

Identify all hazards that may cause the pipeline to stall and to find ways to minimize impact

Structural Hazard
This condition occurs when two instructions require the use of a given hardware at the same time. Two examples:

1.Two access to cache by two different instructions- one for fetch, another for write.

What is the solution?

Structural Hazard [Example 2] What is the solution to this problem?????

Data Hazard

Situation in which the pipeline is stalled because the data to be operated on are delayed for some reason.

Data Hazard
Results obtained when instruction are executed in a pipelined processor must be identical to when same instruction are executed sequentially. Example: A = 3 + A B=4*A Assume A= 3, result for sequential operation: B=24 Result for Pipelined operation: B= 12 ( Oops!!! Answer is wrong)
What to do????????????

Data Hazard Example 2

Mul R2, R3, R4 Add R5,R4,R6

What is the solution to example 2 of data hazard

Solution 1:

Solution for Example 2 of Data hazardOperand Forwarding After decoding instruction, a decision is made to use data forwarding
It is a hardware solution

What is the solution to example 2 of data hazard

Solution 2: Alternatively, we look for software solution, the work of detecting data dependency and dealing is left to the software, Complier i1: Mul R2, R3, R4 NOP NOP i2: Add R5, R4, R6 In NOP, the complier may reorder the instruction and perform useful tasks.

Side effects
In the previous cases, the data dependencies are explicit because the register are named explicitly. In few cases, when a location other than one explicitly named in an instruction as a destination operand is affected, the instruction is said to have a Side Effect

Example: Add R1, R3 AddWithCarry R2, R4 Operation performed: R4=[R2]+[R4]+ Carry - it rise to multiple data dependencies How to handle this situation??

Instructional Hazard

Solution to Cache misses(1/2)

Solution to cache misses(2/2)

Summary

Clarifications contact: camilus@nitc.ac.in