SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM.

Verilog Module

module logicgates(A,B, not1,or2,and2,nor2,nand2,xor2,xnor2);

input A,B;
output not1,or2,and2,nor2,nand2,xor2,xnor2;
reg not1,or2,and2,nor2,nand2,xor2,xnor2;
always@(A or B)
begin
not1 = ~A;
and2 = (A & B);
or2 = A | B;
nand2 = ~(A & B);
nor2 = ~(A | B);
xor2 = A ^ B;
xnor2 = ~(A ^ B);
end
endmodule

Simulated Output:

Post -Place and Route Waveform:

EC1404 - VLSI LAB MANUAL

SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM.

RTL Schematic:

XOR Gate:

Basic gates:

EC1404 - VLSI LAB MANUAL

SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM.

UCF (User Constraints file):

NET "A" LOC = "p74" ;

NET "and2" LOC = "p86" ;
NET "B" LOC = "p76" ;
NET "nand2" LOC = "p89" ;
NET "nor2" LOC = "p87" ;
NET "not1" LOC = "p84" ;
NET "or2" LOC = "p96" ;
NET "xor2" LOC = "p90" ;
NET xnor2 LOC = p85;

EC1404 - VLSI LAB MANUAL

SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM.

EC1404 - VLSI LAB MANUAL

Device utilization summary:

Selected Device

: 3s400tq144-4

Number of Slices

: 4 out of 4656

0%

Number of 4 input LUTs

: 7 out of 9312

0%

Number of IOs

:9

Number of bonded IOBs

: 9 out of 158

5%

Timing Detail :
Timing constraint: Default path analysis
Total number of paths / destination ports: 13 / 7
------------------------------------------------------------------------Delay:

5.998ns (Levels of Logic = 3)

Source:

A (PAD)

Destination:

nor2 (PAD)

Data Path: A to nor2

Gate
Cell:in->out

Net

fanout Delay Delay Logical Name (Net Name)

---------------------------------------- -----------IBUF:I->O

7 1.106 0.754 A_IBUF (A_IBUF)

LUT2:I0->O

1 0.612 0.357 or21 (or2_OBUF)

OBUF:I->O

3.169 or2_OBUF (or2)

---------------------------------------Total

5.998ns (4.887ns logic, 1.111ns route)

(81.5% logic, 18.5% route)

a. Half adder:

Verilog module:
module halfadd(a,b,sum,cy);
input a,b;
output sum,cy;
assign sum = a ^ b;
assign cy = a & b;
endmodule
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SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM.

Simulated Waveform:

Post-Place and Route Simulation:

Device utilization summary:

Selected Device

: 3s400tq144-4

Number of Slices

: 1 out of 4656

0%

Number of 4 input LUTs

: 2 out of 9312

0%

Number of IOs

:4

Number of bonded IOBs

: 4 out of 158

2%

Timing Detail:
Timing constraint: Default path analysis
Total number of paths / destination ports: 4 / 2
------------------------------------------------------------------------Delay:
Source:
Destination:

5.776ns (Levels of Logic = 3)

a (PAD)
cy (PAD)
5

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SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM.

EC1404 - VLSI LAB MANUAL

Data Path: a to cy
Gate
Cell:in->out

Net

fanout Delay Delay Logical Name (Net Name)

---------------------------------------- -----------IBUF:I->O

2 1.106 0.532

a_IBUF (a_IBUF)

LUT2:I0->O

1 0.612 0.357

cy1 (cy_OBUF)

OBUF:I->O

3.169

cy_OBUF (cy)

---------------------------------------Total

5.776ns (4.887ns logic, 0.889ns route)

(84.6% logic, 15.4% route)

RTL Schematic:

UCF (User Constraints File):

NET "a" LOC = "p74" ;
NET "b" LOC = "p76" ;
NET "sum" LOC = "p86" ;
NET "cy" LOC = "p87" ;

SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM.

b. Full Adder:

Verilog Module:
module fuladd(a,b,c, sum,cy);
input a,b,c;
output sum,cy;
assign sum = (a^b)^c;
assign cy = (a&b)|(b&c)|(a&c);
endmodule

Simulated Waveform:

Post Place and Route Waveform:

EC1404 - VLSI LAB MANUAL

SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM.

RTL Schematic:

Device utilization summary:

Selected Device

: 3s400tq144-4

Number of Slices

: 1 out of 4656

0%

Number of 4 input LUTs

: 2 out of 9312

0%

Number of IOs

:5

Number of bonded IOBs

: 5 out of 158

3%

EC1404 - VLSI LAB MANUAL

SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM.

EC1404 - VLSI LAB MANUAL

Timing Detail:
Timing constraint: Default path analysis
Total number of paths / destination ports: 6 / 2
------------------------------------------------------------------------Delay:
Source:

5.776ns (Levels of Logic = 3)

b (PAD)

Destination:

cy (PAD)

Data Path: b to cy
Gate
Cell:in->out

Net

fanout Delay Delay Logical Name (Net Name)

---------------------------------------- -----------IBUF:I->O

1.106

LUT3:I0->O

0.612 0.357 cy1 (cy_OBUF)

OBUF:I->O

0.532 b_IBUF (b_IBUF)

3.169 cy_OBUF (cy)

---------------------------------------Total

5.776ns (4.887ns logic, 0.889ns route)

(84.6% logic, 15.4% route)

UCF (User Constraints file):

NET "a" LOC = "p74" ;

NET "b" LOC = "p76" ;
NET "c" LOC = "p77" ;
NET "cy" LOC = "p86" ;
NET "sum" LOC = "p87" ;

c. Half Subtractor:
Verilog Module:
module halfsub(a,b,diff,borr);
input a,b;
output diff,borr;
assign diff = a ^ b;
assign borr = (~a) & b;
endmodule

SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM.

EC1404 - VLSI LAB MANUAL

Simulated waveform:

Post Place and Route Simulated waveform:

Device utilization summary:

Selected Device

: 3s400tq144-4

Number of Slices

: 1 out of 4656

0%

Number of 4 input LUTs

: 2 out of 9312

0%

Number of IOs

:4

Number of bonded IOBs

: 4 out of 158

2%

Timing Detail:
Timing constraint: Default path analysis
Total number of paths / destination ports: 4 / 2
------------------------------------------------------------------------Delay:
Source:
Destination:

5.776ns (Levels of Logic = 3)

a (PAD)
borr (PAD)

Data Path: a to borr

Gate
Cell:in->out

Net

fanout Delay Delay Logical Name (Net Name)

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SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM.

---------------------------------------- -----------IBUF:I->O

2 1.106 0.532

a_IBUF (a_IBUF)

LUT2:I0->O

1 0.612 0.357

borr1 (borr_OBUF)

OBUF:I->O

3.169

borr_OBUF (borr)

---------------------------------------Total

5.776ns (4.887ns logic, 0.889ns route)

(84.6% logic, 15.4% route)

RTL Schematic:

UCF(User Constraints File):

NET "a" LOC = "p74";

NET "b" LOC = "p76";
NET "borr" LOC = "p86";
NET "diff" LOC = "p87";

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d. Full Subtractor:

Verilog Module:
module fullsub(a,b,c,diff,borr);
input a,b,c;
output diff,borr;
assign diff=(a^b)^c;
assign borr = ((~(a^b))&c)|((~a)&b);
endmodule

Simulated Waveform:

POST PLACE AND ROUTE REPORT:

Device utilization summary:

Selected Device

: 3s400tq144-4

Number of Slices

: 1 out of 4656

0%

Number of 4 input LUTs

: 2 out of 9312

0%

Number of IOs

:5

Number of bonded IOBs

: 5 out of 158
12

3%

EC1404 - VLSI LAB MANUAL

SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM.

EC1404 - VLSI LAB MANUAL

Timing Detail:
Timing constraint: Default path analysis
Total number of paths / destination ports: 6 / 2
------------------------------------------------------------------------Delay:

5.776ns (Levels of Logic = 3)

Source:

z (PAD)

Destination:

borr (PAD)

Data Path: z to borr

Gate
Cell:in->out

Net

fanout Delay Delay Logical Name (Net Name)

---------------------------------------- -----------IBUF:I->O

2 1.106 0.532

z_IBUF (z_IBUF)

LUT3:I0->O

1 0.612 0.357

borr1 (borr_OBUF)

OBUF:I->O

3.169

borr_OBUF (borr)

---------------------------------------Total

5.776ns (4.887ns logic, 0.889ns route)

(84.6% logic, 15.4% route)

RTL Schematic:

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SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM.

UCF (User Constraints File):

NET "borr LOC = "p84" ;
NET "diff" LOC = "p86" ;
NET "x" LOC = "p74" ;
NET "y" LOC = "p76" ;
NET "z" LOC = "p77" ;
a. Parallel Adder
Verilog Module:
module parallel_adder(a,b,cin,sum,cout);
input [0:3] a,b;
input cin;
output [0:3]sum;
output cout;
wire [0:2]w;
fulladd f1(a[0],b[0],cin,sum[0],w[0]),
f2(a[1],b[1],w[0],sum[1],w[1]),
f3(a[2],b[2],w[1],sum[2],w[2]),
f4(a[3],b[3],w[2],sum[3],cout);
endmodule
Simulated Output:

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Post Place and Route Waveform:

Device utilization summary:

Selected Device

: 3s400tq144-4

Number of Slices

: 4 out of 4656

0%

Number of 4 input LUTs

: 8 out of 9312

0%

Number of IOs

: 14

Number of bonded IOBs

: 14 out of 158

8%

Timing Detail:
Timing constraint: Default path analysis
Total number of paths / destination ports: 33 / 5
------------------------------------------------------------------------Delay:

8.959ns (Levels of Logic = 6)

Source:

b<0> (PAD)

Destination:

cout (PAD)

Data Path: b<0> to cout

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SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM.

Gate
Cell:in->out

EC1404 - VLSI LAB MANUAL

Net

fanout Delay Delay Logical Name (Net Name)

---------------------------------------- -----------IBUF:I->O

2 1.106 0.532

b_0_IBUF (b_0_IBUF)

LUT3:I0->O

2 0.612 0.449

f1/cy1 (w<0>)

LUT3:I1->O

2 0.612 0.449

f2/cy1 (w<1>)

LUT3:I1->O

2 0.612 0.449

f3/cy1 (w<2>)

LUT3:I1->O

1 0.612 0.357

f4/cy1 (cout_OBUF)

OBUF:I->O

3.169

cout_OBUF (cout)

---------------------------------------Total

8.959ns (6.723ns logic, 2.236ns route)

(75.0% logic, 25.0% route)

RTL Schematic:

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SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM.

UCF (User Constraints File):

NET "a<0>" LOC = "p74" ;

NET "a<1>" LOC = "p75" ;
NET "a<2>" LOC = "p76" ;
NET "a<3>" LOC = "p77" ;
NET "b<0>" LOC = "p78" ;
NET "b<1>" LOC = "p82" ;
NET "b<2>" LOC = "p80" ;
NET "b<3>" LOC = "p83" ;
NET "cin" LOC = "p100" ;
NET "cout" LOC = "p84" ;
NET "s<0>" LOC = "p86" ;
NET "s<1>" LOC = "p87" ;
NET "s<2>" LOC = "p89" ;
NET "s<3>" LOC = "p90" ;

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SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM.

b. 4 bit binary adder cum Subtractor:

Verilog Module:
module fourbit(a,b,cin,s,cout);
input [0:3] a,b; input cin;
output [0:3]s;
output cout;
wire [0:3]w;
xor x1(w[0],b[0],cin),
x2(w[1],b[1],cin),
x3(w[2],b[2],cin),
x4(w3],b[3],cin);
parallel_adder p1(a,w,cin,s,cout);
endmodule

Simulated Output:

18

EC1404 - VLSI LAB MANUAL

SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM.

Post Place and Route Waveform:

Device utilization summary:

Selected Device

: 3s400tq144-4

Number of Slices

: 4 out of 4656

0%

Number of 4 input LUTs

: 8 out of 9312

0%

Number of IOs

: 14

Number of bonded IOBs

: 14 out of 158

8%

Timing Detail:

Timing constraint: Default path analysis

Total number of paths / destination ports: 41 / 5
------------------------------------------------------------------------Delay:
Source:
Destination:

8.900ns (Levels of Logic = 6)

cin (PAD)
cout (PAD)
19

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EC1404 - VLSI LAB MANUAL

Data Path: cin to cout

Gate
Cell:in->out

Net

fanout Delay Delay Logical Name (Net Name)

---------------------------------------- -----------IBUF:I->O

7 1.106 0.671

cin_IBUF (cin_IBUF)

LUT3:I1->O

2 0.612 0.383

p1/f1/cy1 (p1/w<0>)

LUT4:I3->O

2 0.612 0.383

p1/f2/cy1 (p1/w<1>)

LUT4:I3->O

2 0.612 0.383

p1/f3/cy1 (p1/w<2>)

LUT4:I3->O

1 0.612 0.357

p1/f4/cy1 (cout_OBUF)

OBUF:I->O

3.169

cout_OBUF (cout)

---------------------------------------Total

8.900ns (6.723ns logic, 2.177ns route)

(75.5% logic, 24.5% route)

RTL Schematic:

20

SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM.

21

EC1404 - VLSI LAB MANUAL

SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM.

UCF (User Constraints File):

NET "a<0>" LOC = "p74" ;
NET "a<1>" LOC = "p76" ;
NET "a<2>" LOC = "p77" ;
NET "a<3>" LOC = "p78" ;
NET "b<0>" LOC = "p82" ;
NET "b<1>" LOC = "p80" ;
NET "b<2>" LOC = "p83" ;
NET "b<3>" LOC = "p75" ;
NET "cin" LOC = "p100" ;
NET "cout" LOC = "p84" ;
NET "sum<0>" LOC = "p87" ;
NET "sum<1>" LOC = "p86" ;
NET "sum<2>" LOC = "p89" ;
NET "sum<3>" LOC = "p90" ;
Verilog Module:
module magcomp(a,b,x,y,z);
input [0:3]a,b;
output x,y,z;
assign x = (a == b),
y = (a < b),
z = (a > b);
endmodule

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SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM.

Simulated Output:

Post Place and Route waveform:

23

EC1404 - VLSI LAB MANUAL

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EC1404 - VLSI LAB MANUAL

Device utilization summary:

Selected Device

: 3s400tq144-4

Number of Slices

: 5 out of 4656

0%

Number of 4 input LUTs

: 9 out of 9312

0%

Number of IOs

: 11

Number of bonded IOBs

: 11 out of 158

6%

Timing Detail:

Timing constraint: Default path analysis

Total number of paths / destination ports: 32 / 3
------------------------------------------------------------------------Delay:

6.972ns (Levels of Logic = 4)

Source:
Destination:

a<3> (PAD)
x (PAD)

Data Path: a<3> to x

Gate
Cell:in->out

Net

fanout Delay Delay Logical Name (Net Name)

---------------------------------------- -----------IBUF:I->O

5 1.106 0.690

a_3_IBUF (a_3_IBUF)

LUT4:I0->O

1 0.612 0.426

x453 (x4_map21)

LUT2:I1->O

1 0.612 0.357

x454 (x_OBUF)

OBUF:I->O

3.169

x_OBUF (x)

---------------------------------------Total

6.972ns (5.499ns logic, 1.473ns route)

(78.9% logic, 21.1% route)

24

SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM.

RTL Schematic:

UCF (User Constraints File):

NET "a<0>" LOC = "p74" ;

NET "a<1>" LOC = "p76" ;
NET "a<2>" LOC = "p77" ;
NET "a<3>" LOC = "p78" ;
NET "b<0>" LOC = "p100" ;
NET "b<1>" LOC = "p80" ;
NET "b<2>" LOC = "p82" ;
NET "b<3>" LOC = "p83" ;
NET "x" LOC = "p84" ;
NET "y" LOC = "p86" ;
NET "z" LOC = "p87" ;

25

EC1404 - VLSI LAB MANUAL

SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM.

Verilog Module:
module paritygen(x,y,z,p,c);
input x,y,z;
inout p;
output c;
wire w1,w2,w3;
xor x1(w1,x,y),x2(w2,w1,z);
not n1(p,w2);
xor x3(w3,w2,p);
not n2(c,w3);
endmodule

Simulated Output:

Post Place and Route output:

26

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EC1404 - VLSI LAB MANUAL

Device utilization summary:

Selected Device

: 3s400tq144-4

Number of Slices

: 1 out of 4656

0%

Number of 4 input LUTs

: 1 out of 9312

0%

Number of IOs

:5

Number of bonded IOBs

: 5 out of 158

3%

Timing Detail:
Timing constraint: Default path analysis
Total number of paths / destination ports: 3 / 1
------------------------------------------------------------------------Delay:

5.753ns (Levels of Logic = 3)

Source:

y (PAD)

Destination:

p (PAD)

Data Path: y to p
Gate
Cell:in->out

Net

fanout Delay Delay Logical Name (Net Name)

---------------------------------------- -----------IBUF:I->O

1 1.106

0.509

y_IBUF (y_IBUF)

LUT3:I0->O

1 0.612

0.357

p1 (p_OBUF)

3.169

p_OBUF (p)

OBUF:I->O

---------------------------------------Total

5.753ns (4.887ns logic, 0.866ns route)

(84.9% logic, 15.1% route)

RTL Schematic:

27

SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM.

UCF (User Constraint File):

NET "c" LOC = "p84" ;

NET "p" LOC = "p74" ;
NET "x" LOC = "p75" ;
NET "y" LOC = "p76" ;
NET "z" LOC = "p77" ;

Verilog Module:

module multi(m,a,b);
input [0:1]a,b;
output [0:3] m;
wire [0:3]w;
and a1(m[0],a[0],b[0]),
a2(w[0],a[1],b[1]),
a3(w[1],a[0],b[1]),
a4(w[2],a[1],b[1]);
halfadd h1(m[1],w[3],w[0],w[1]),
h2(m[2],m[3],w[3],[w2]);
endmodule

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Simulated Output:

Post-Place and Route Output:

Device utilization summary:

Selected Device

: 3s400tq144-4

Number of Slices

: 1 out of 4656

0%

Number of 4 input LUTs

: 1 out of 9312

0%

Number of IOs

:8

Number of bonded IOBs

: 6 out of 158
29

3%

EC1404 - VLSI LAB MANUAL

SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM.

EC1404 - VLSI LAB MANUAL

Timing Detail:

Timing constraint: Default path analysis

Total number of paths / destination ports: 2 / 1
------------------------------------------------------------------------Delay:
Source:
Destination:

5.753ns (Levels of Logic = 3)

a<0> (PAD)
m<0> (PAD)

Data Path: a<0> to m<0>

Gate
Cell:in->out

Net

fanout Delay Delay Logical Name (Net Name)

------------------------------------------------------------------------------IBUF:I->O

1 1.106 0.509 a_0_IBUF (a_0_IBUF)

LUT2:I0->O

1 0.612 0.357 m_0_and00001 (m_0_OBUF)

OBUF:I->O
Total

3.169 m_0_OBUF (m<0>)

5.753ns (4.887ns logic, 0.866ns route) (84.9% logic, 15.1% route)

RTL Schematic:

30

SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM.

UCF (User Constraints File):

NET "a<0>" LOC = "p74" ;

NET "a<1>" LOC = "p76" ;
NET "b<0>" LOC = "p77" ;
NET "b<1>" LOC = "p78" ;
NET "m<0>" LOC = "p84" ;
NET "m<1>" LOC = "p86" ;
NET "m<2>" LOC = "p87" ;
NET "m<3>" LOC = "p89" ;

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SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM.

a. 4 Bit Binary to Gray Code Converter:

Verilog Module:

module bingray(a,b,c,d,w,x,y,z);
input a,b,c,d;
output w,x,y,z;
buf b1(w,a);
xor x1(x,a,b),
x2(y,b,c),
x3(z,c,d);
endmodule
Simulated Output:

Post Place and Route Simulated output:

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EC1404 - VLSI LAB MANUAL

Device utilization summary:

Selected Device

: 3s400tq144-4

Number of Slices

: 2 out of 4656

0%

Number of 4 input LUTs

: 3 out of 9312

0%

Number of IOs

:8

Number of bonded IOBs

: 8 out of 158

5%

Timing Detail:
Timing constraint: Default path analysis
Total number of paths / destination ports: 7 / 4
Delay:
Source:
Destination:

5.776ns (Levels of Logic = 3)

b (PAD)
x (PAD)

Data Path: b to x
Gate Net
Cell:in->out

fanout

Delay Delay Logical Name (Net Name)

-----------------------------------------------------------------------------------IBUF:I->O

1.106 0.532 b_IBUF (b_IBUF)

LUT2:I0->O

0.612 0.357 Mxor_x_Result1 (x_OBUF)

OBUF:I->O
Total

3.169 x_OBUF (x)

5.776ns (4.887ns logic, 0.889ns route)
(84.6% logic, 15.4% route)

RTL Schematic:

33

SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM.

UCF (User Constraints File):

NET "a" LOC = "p74" ;
NET "b" LOC = "p76" ;
NET "c" LOC = "p77" ;
NET "d" LOC = "p78" ;
NET "w" LOC = "p84" ;
NET "x" LOC = "p86" ;
NET "y" LOC = "p87" ;
NET "z" LOC = "p89" ;

b. 4 Bit Gray to Binary Code Converter

Verilog Module:
module graybin(a,b,c,d,w,x,y,z);
input a,b,c,d;
output w,x,y,z;
wire x,y,z;
buf b1(w,a);
xor x1(x,w,b),
x2(y,x,c),
x3(z,y,d);
endmodule

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Simulated Output:

Post Place and Route Simulated Output:

Device utilization summary:

Selected Device

: 3s400tq144-4

Number of Slices

: 2 out of 4656

0%

Number of 4 input LUTs

: 3 out of 9312

0%

Number of IOs

:8

Number of bonded IOBs

: 8 out of 158

35

5%

EC1404 - VLSI LAB MANUAL

SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM.

EC1404 - VLSI LAB MANUAL

Timing Detail:
Timing constraint: Default path analysis
Total number of paths / destination ports: 10 / 4
------------------------------------------------------------------------Delay:

5.847ns (Levels of Logic = 3)

Source:

b (PAD)

Destination:

x (PAD)

Data Path: b to x
Gate
Cell:in->out

Net

fanout Delay Delay Logical Name (Net Name)

---------------------------------------- -----------------------------------------IBUF:I->O

1.106 0.603

b_IBUF (b_IBUF)

LUT2:I0->O

0.612 0.357

Mxor_x_Result1 (x_OBUF)

OBUF:I->O

3.169

x_OBUF (x)

----------------------------------------------------------------------------------Total

5.847ns (4.887ns logic, 0.960ns route) (83.6% logic, 16.4% route)

RTL Schematic:

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SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM.

UCF (User Constraints File):

NET "a" LOC = "p74" ;

NET "b" LOC = "p76" ;
NET "c" LOC = "p75" ;
NET "d" LOC = "p77" ;
NET "w" LOC = "p84" ;
NET "x" LOC = "p86" ;
NET "y" LOC = "p87" ;
NET "z" LOC = "p89" ;

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Multiplexer
Verilog Module:
module mux(en,a,sel,y);
input en;
input [3:0]a;
input [1:0]sel;
output y;
reg y;
always@(en or a)
begin
if(!en)
y = 1'b0;
else case(sel)
2'b00: y=a[0];
2'b01: y=a[1];
2'b10: y=a[2];
2'b11: y=a[3];
endcase
end
endmodule

Simulated Output:

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EC1404 - VLSI LAB MANUAL

RTL Schematic:

Device utilization summary:

Selected Device

: 3s400tq144-4

Number of Slices

: 1 out of 4656

0%

Number of 4 input LUTs

: 2 out of 9312

0%

Number of IOs

:8

Number of bonded IOBs

: 8 out of 158

5%

Timing Detail:

Timing constraint: Default path analysis

Total number of paths / destination ports: 9 / 1
Delay:

6.054ns (Levels of Logic = 4)

Source:
Destination:

sel<0> (PAD)
y (PAD)

Data Path: sel<0> to y

Gate
Cell:in->out

Net

fanout Delay Delay Logical Name (Net Name)

---------------------------------------- -----------IBUF:I->O

1.106

0.532

LUT4:I0->O

0.612 0.000

sel_0_IBUF (sel_0_IBUF)
y_F (N6)
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SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM.

MUXF5:I0->O 1

0.278 0.357

y (y_OBUF)

3.169

y_OBUF (y)

OBUF:I->O

EC1404 - VLSI LAB MANUAL

---------------------------------------Total

6.054ns (5.165ns logic, 0.889ns route) (85.3% logic, 14.7% route)

RTL Schematic:

UCF (User Constraints File):

NET "a<0>" LOC = "p74" ;

NET "a<1>" LOC = "p76" ;
NET "a<2>" LOC = "p77" ;
NET "a<3>" LOC = "p78" ;
NET "en" LOC = "p82" ;
NET "sel<0>" LOC = "p80" ;
NET "sel<1>" LOC = "p83" ;
NET "y" LOC = "p84" ;

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SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM.

Decoder
Verilog Module:
module decoder(en, ain, yout);
input en;
input [0:1] ain;
output [0:3] yout;
reg [0:3] yout;
always@(en or ain)
begin
if(!en)
yout = 4'b0;
else
case (ain)
2'b00: yout = 4'b0001;
2'b01: yout = 4'b0010;
2'b10: yout = 4'b0100;
2'b11: yout = 4'b1000;
endcase
end
endmodule

Simulated output:

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Post Place and Route Simulated Output:

Device Utilization Summary:

Selected Device:

3s400tq144-4

Number of Slices:

2 out of 3584

0%

Number of 4 input LUTs:

4 out of 7168

0%

Number of IOs:

Number of bonded IOBs:

7 out of

97

7%

RTL Schematic:

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EC1404 - VLSI LAB MANUAL

Timing Details:
Delay:

9.073ns (Levels of Logic = 3)

Source:

en (PAD)

Destination:

yout<0> (PAD)

Data Path: en to yout<0>

Gate
Cell:in->out

Net

fanout Delay Delay Logical Name (Net Name)

---------------------------------------------------------------------------------IBUF:I->O

4 0.821 1.256 en_IBUF (en_IBUF)

LUT3:I0->O

1 0.551 0.801 yout<0>1 (yout_0_OBUF)

OBUF:I->O

5.644 yout_0_OBUF (yout<0>)

---------------------------------------------------------------------------------Total

9.073ns (7.016ns logic, 2.057ns route)

(77.3% logic, 22.7% route)

UCF (User Constraints File):

NET en LOC =p74;
NET ain<0> LOC =p76;
NET ain<1> LOC =p77;
NET yout<0> LOC =p84;
NET yout<1> LOC =p85;
NET yout<2> LOC =p86;
NET yout<3> LOC =p87;

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SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM.

a. Encoder
Verilog Module:
module encoder(en, ain, out);
input en;
input [0:7] ain;
output [0:2] out;
reg [0:2] out;
always @(en or ain)
begin
if(!en)
out = 3'b0;
else
case(ain)
8'b00000001:out = 3'b000;
8'b00000010:out = 3'b001;
8'b00000100:out = 3'b010;
8'b00001000:out = 3'b011;
8'b00010000:out = 3'b100;
8'b00100000:out = 3'b101;
8'b01000000:out = 3'b110;
8'b10000000:out = 3'b111;
default:out = 3'b000;
endcase
end
endmodule

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Simulated output:

Post place and route simulated output:

45

EC1404 - VLSI LAB MANUAL

SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM.

RTL Schematic:

Sub Section:

46

EC1404 - VLSI LAB MANUAL

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EC1404 - VLSI LAB MANUAL

Device Utilization Summary:

Selected Device :

3s400tq144-4

Number of Slices:

4 out of 3584

0%

Number of 4 input LUTs:

8 out of 7168

0%

Number of IOs:

12

Number of bonded IOBs:

12 out of

97 12%

Timing Details:
Delay:

11.988ns (Levels of Logic = 5)

Source:
Destination:

ain<0> (PAD)
out<0> (PAD)

Data Path: ain<0> to out<0>

Gate
Cell:in->out

Net

fanout Delay Delay Logical Name (Net Name)

------------------------------------------------------------------------------------IBUF:I->O

3 0.821 1.246 ain_0_IBUF (ain_0_IBUF)

LUT4:I0->O

1 0.551 0.827 out<0>84 (out<0>_map24)

LUT4:I3->O

1 0.551 0.996 out<0>106 (out<0>_map26)

LUT3:I1->O

1 0.551 0.801 out<0>123 (out_0_OBUF)

OBUF:I->O

5.644 out_0_OBUF (out<0>)

-------------------------------------------------------------------------------Total

11.988ns (8.118ns logic, 3.870ns route)

(67.7% logic, 32.3% route)
47

SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM.

UCF (User Constraints File):

NET en LOC = p74;

NET ain<0> LOC = p76;
NET ain<1> LOC = p77;
NET ain<2> LOC = p79;
NET ain<3> LOC = p78;
NET ain<4> LOC = p83;
NET ain<5> LOC = p82;
NET ain<6> LOC = p84;
NET ain<7> LOC = p85;
NET out<0> LOC = p104;
NET out<1> LOC = p125;
NET out<2> LOC = p122;

Verilog Module:
module halfmux(a,b, sum,cy);
input a,b;
output sum,cy;
wire [0:1] w;
assign w = {a,b};
mux m1(0,1,1,0,w,sum),m2(0,0,0,1,w,cy);
endmodule

Mux Module:
module halfmux(a,b, sum,cy);
input a,b;
output sum,cy;
wire [0:1] w;
assign w = {a,b};
mux m1(0,1,1,0,w,sum),m2(0,0,0,1,w,cy);
endmodule

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Simulated Output:

Post Place and Route Simulated output:

RTL Schematic:

Device Utilization Summary:

Selected Device

: 3s400tq144-4

Number of Slices

: 1 out of 3584

0%

Number of 4 input LUTs

: 2 out of 7168

0%

Number of IOs

:4

Number of bonded IOBs

: 4 out of

97
49

4%

EC1404 - VLSI LAB MANUAL

SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM.

EC1404 - VLSI LAB MANUAL

Timing Detail:
Delay:
Source:

9.033ns (Levels of Logic = 3)

b (PAD)

Destination:

cy (PAD)

Data Path: b to cy
Gate
Cell:in->out

Net

fanout Delay Delay Logical Name (Net Name)

---------------------------------------- -----------IBUF:I->O

0.821 1.216

b_IBUF (b_IBUF)

LUT2:I0->O

0.551 0.801

m2/Mmux_y11 (cy_OBUF)

OBUF:I->O

5.644

cy_OBUF (cy)

---------------------------------------Total

9.033ns (7.016ns logic, 2.017ns route)

(77.7% logic, 22.3% route)

UCF (User Constraints File):

NET a LOC = p74;

NET b LOC = p76;
NET sum LOC = p84;
NET cy LOC = p85;

a. JK Flip Flop

Verilog Module:
module jkff(q,qbar,j,k,clk);
output q,qbar;
input j,k,clk;
reg q=1'b0;
always @(negedge clk)
if(j==0&&k==0)
q=q;
else if(j==0&&k==1)
q = 0;
50

SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM.

else if(j==1&&k==0)
q = 1;
else
q=~q;
end
assign qbar = ~q;
endmodule

Simulated Output:

Post Place and Route Simulated Output:

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RTL Schematic:

Device utilization summary:

Selected Device

: 3s400tq144-4

Number of Slices

: 2 out of 2448

0%

Number of Slice Flip Flops : 1 out of 4896

0%

Number of 4 input LUTs

: 3 out of 4896

0%

Number of IOs

:5

Number of bonded IOBs

: 5 out of 158

3%

Number of GCLKs

: 1 out of

4%

24

Timing Detail:
Timing constraint: Default period analysis for Clock 'clk'
Clock period: 1.875ns (frequency: 533.234MHz)
Total number of paths / destination ports: 1 / 1
------------------------------------------------------------------------Delay:
Source:

1.875ns (Levels of Logic = 1)

q (FF), Destination:

q (FF)
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Source Clock:

EC1404 - VLSI LAB MANUAL

clk falling, Destination Clock: clk falling

Data Path: q to q
Gate
Cell:in->out

Net

fanout Delay Delay Logical Name (Net Name)

---------------------------------------- -----------FDE_1:C->Q

3 0.514 0.481

q (q_OBUF)

LUT3:I2->O

1 0.612 0.000

q_mux00001 (q_mux0000)

FDE_1:D

0.268

---------------------------------------Total

1.875ns (1.394ns logic, 0.481ns route) (74.3% logic, 25.7% route)

UCF (User Constraints File):

NET clk LOC = p52;

NET "j" LOC = "p74";
NET "k" LOC = "p76";
NET "q" LOC = "p84";
NET "qbar" LOC = "p86";

b. T Flip Flop
Verilog Module:
module tff(q,qbar,t,clk);
output q,qbar;
input t,clk;
reg q = 0;
always @(posedge clk)
if(t)
q = ~q;
else
q = q;
assign qbar = ~q;
endmodule

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SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM.

Simulated Output:

Post Place and Route Simulated Output:

RTL Schematic:

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EC1404 - VLSI LAB MANUAL

Device utilization summary:

Selected Device

: 3s400tq144-4

Number of Slices

: 1 out of 2448

0%

Number of Slice Flip Flops : 1 out of 4896

0%

Number of 4 input LUTs

: 1 out of 4896

0%

Number of IOs

:4

Number of bonded IOBs

: 4 out of 158

2%

Number of GCLKs

: 1 out of

4%

24

Timing Detail:
Timing constraint: Default period analysis for Clock 'clk'
Clock period: 2.154ns (frequency: 464.274MHz)
Total number of paths / destination ports: 1 / 1
------------------------------------------------------------------------Delay:

2.154ns (Levels of Logic = 1)

Source:

q (FF), Destination:

Source Clock:

q (FF)

clk rising, Destination Clock: clk rising

Data Path: q to q
Gate
Cell:in->out

Net

fanout Delay Delay Logical Name (Net Name)

---------------------------------------- -----------FDE:C->Q

2 0.514 0.380

q (q_OBUF)

INV:I->O

2 0.612 0.380

qbar1_INV_0 (qbar_OBUF)

FDE:D
Total

0.268

2.154ns (1.394ns logic, 0.760ns route)

(64.7% logic, 35.3% route)

UCF (User Constraints File):

NET clk LOC = p52 ;
NET "t" LOC = "p74" ;
NET "q" LOC = "p84" ;
NET "qbar" LOC = "p86" ;

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SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM.

c. D Flip Flop

Verilog Module:
module dff(q,d,clk);
input d,clk;
output q;
reg q;
always @(posedge clk)
q = d;
endmodule
Simulated Output:

Post Place and Route Simulated Output:

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EC1404 - VLSI LAB MANUAL

RTL Schematic:

Device utilization summary:

Selected Device

: 3s400tq144-4

Number of Slices

: 1 out of 2448

0%

Number of Slice Flip Flops : 2 out of 4896

0%

Number of 4 input LUTs

: 1 out of 4896

0%

Number of IOs

:4

Number of bonded IOBs

: 4 out of 158

IOB Flip Flops

2%

:2

Number of GCLKs

: 1 out of

24

4%

Timing Detail:
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Total number of paths / destination ports: 2 / 2
------------------------------------------------------------------------Offset:
Source:
Destination:

1.754ns (Levels of Logic = 1)

d (PAD)
q (FF)

Destination Clock: clk rising

Data Path: d to q
Gate
Cell:in->out

Net

fanout Delay Delay Logical Name (Net Name)

---------------------------------------- -----------IBUF:I->O

2 1.106 0.380 d_IBUF (d_IBUF)

57

SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM.

FD:D

0.268

---------------------------------------Total

1.754ns (1.374ns logic, 0.380ns route)

(78.3% logic, 21.7% route)

UCF (User Constraints File):

NET clk LOC = p52 ;
NET "d" LOC = "p74" ;
NET "q" LOC = "p84" ;
NET "qbar" LOC = "p86" ;

Verilog Module:

module shiftreg(d,clk,z);
input d,clk;
output z;
parameter NUM = 4;
reg [1:NUM]q;
integer p;
always @(negedge clk)
begin
for(p=1;p<NUM;p=p+1)
q[p+1] = q[p];
q[1]=d;
end
assign z=q[NUM];
endmodule

58

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EC1404 - VLSI LAB MANUAL

Simulated Output:

Post Place and Route Simulated Output:

RTL Schematic:

Device utilization summary:

Selected Device

: 3s400tq144-4

Number of Slices

: 1 out of 2448

0%

Number of Slice Flip Flops

: 1 out of 4896

0%

Number of 4 input LUTs

: 1 out of 4896

0%

Number used as logic

:0

Number used as Shift registers

:1

Number of IOs

:3

Number of bonded IOBs

: 3 out of 158

1%

Number of GCLKs

: 1 out of

4%

59

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SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM.

EC1404 - VLSI LAB MANUAL

Timing Detail:

Timing constraint: Default period analysis for Clock 'clk'

Clock period: 3.492ns (frequency: 286.369MHz)
Total number of paths / destination ports: 1 / 1
------------------------------------------------------------------------Delay:
Source:
Destination:
Source Clock:

3.492ns (Levels of Logic = 0)

Mshreg_q_4 (FF)
q_4 (FF)
clk falling

Destination Clock: clk falling

Data Path: Mshreg_q_4 to q_4
Gate
Cell:in->out

Net

fanout Delay Delay Logical Name (Net Name)

---------------------------------------- -----------SRL16_1:CLK->Q

1 3.224 0.000 Mshreg_q_4 (Mshreg_q_4)

FD_1:D

0.268

q_4

---------------------------------------Total

3.492ns (3.492ns logic, 0.000ns route)

(100.0% logic, 0.0% route)

UCF (User Constraints File):

NET clk LOC = p52;

NET "d" LOC = "p74";
NET "z" LOC = "p84";

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SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM.

a. Down Counter:

Verilog Module:
module downcounter(q,clk);
output [0:3]q;
input clk;
wire w2,w3,w4,w5,w6;
not n1(w4,q[1]),
n2(w5,q[2]),
n3(w6,q[3]);
and a1(w2,w5,w6),
a2(w3,w2,w4);
tff t0(q[3],1,clk),
t1(q[2],w6,clk),
t2(q[1],w2,clk),
t3(q[0],w3,clk);
endmodule

TFF:
module tff(q,qbar,t,clk);
output q,qbar;
input t,clk;
reg q = 0;
always @(posedge clk)
if(t)
q = ~q;
else
q = q;
assign qbar = ~q;
endmodule

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Simulated Output:

Post Place and Route Simulated Output:

RTL Schematic:

62

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Device utilization summary:

Selected Device

: 3s400tq144-4

Number of Slices

: 3 out of 2448

0%

Number of Slice Flip Flops : 4 out of 4896

0%

Number of 4 input LUTs

: 6 out of 4896

0%

Number of IOs

:5

Number of bonded IOBs

: 5 out of 158

3%

Number of GCLKs

: 1 out of

4%

24

Timing Detail:

Timing constraint: Default period analysis for Clock 'clk'

Clock period: 2.617ns (frequency: 382.124MHz)
Total number of paths / destination ports: 10 / 7
Delay:
Source:
Source Clock:

2.617ns (Levels of Logic = 1)

t1/q (FF), Destination:

t2/q (FF)

clk rising, Destination Clock: clk rising

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EC1404 - VLSI LAB MANUAL

Data Path: t1/q to t2/q

Gate
Cell:in->out

Net

fanout Delay Delay Logical Name (Net Name)

---------------------------------------- -----------FDE:C->Q

4 0.514 0.651 t1/q (t1/q)

LUT2:I0->O

1 0.612 0.357 w21 (w2)

FDE:CE

0.483

t2/q

---------------------------------------Total

2.617ns (1.609ns logic, 1.008ns route)

(61.5% logic, 38.5% route)

UCF (User Constraints File):

NET clk LOC = p52 ;

NET "q[0]" LOC = "p84" ;
NET "q[1]" LOC = "p86" ;
NET "q[2]" LOC = "p87" ;
NET "q[3]" LOC = "p88" ;

b. UP Counter:

Verilog Module:

module upcounter(q,clk);
output [0:3]q;
input clk;
wire w2,w3;
and a1(w2,q[2],q[3]),
a2(w3,w2,q[1]);
tff t0(q[3],,1,clk),
t1(q[2],,q[3],clk),
t2(q[1],,w2,clk),
t3(q[0],,w3,clk);
endmodule
64

SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM.

TFF:
module tff(q,qbar,t,clk);
output q,qbar;
input t,clk;
reg q = 0;
always @(posedge clk)
if(t)
q = ~q;
else
q = q;
assign qbar = ~q;
endmodule
Simulated Output:

Post Place and Route Simulated Output:

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RTL Schematic:

Device utilization summary:

Selected Device

: 3s400tq144-4

Number of Slices

: 3 out of 2448

0%

Number of Slice Flip Flops : 4 out of 4896

0%

Number of 4 input LUTs

: 6 out of 4896

0%

Number of IOs

:5

Number of bonded IOBs

: 5 out of 158

3%

Number of GCLKs

: 1 out of

4%

24

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EC1404 - VLSI LAB MANUAL

Timing Detail:

Timing constraint: Default period analysis for Clock 'clk'

Clock period: 2.617ns (frequency: 382.124MHz)
Total number of paths / destination ports: 10 / 7
------------------------------------------------------------------------Delay:

2.617ns (Levels of Logic = 1)

Source:
Source Clock:

t1/q (FF), Destination:

t2/q (FF)

clk rising, Destination Clock: clk rising

Data Path: t1/q to t2/q

Gate
Cell:in->out

Net

fanout Delay Delay Logical Name (Net Name)

---------------------------------------- -----------FDE:C->Q

4 0.514 0.651 t1/q (t1/q)

LUT2:I0->O

1 0.612 0.357 w21 (w2)

FDE:CE

0.483

Total

t2/q

2.617ns (1.609ns logic, 1.008ns route)

(61.5% logic, 38.5% route)

UCF (User Constraints File):

NET clk LOC = p52 ;

NET "q[0]" LOC = "p84" ;
NET "q[1]" LOC = "p86" ;
NET "q[2]" LOC = "p87" ;
NET "q[3]" LOC = "p88" ;

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SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM.

Verilog Module:
module asdowncounter(q,clk);
output [3:0]q;
input clk;
tff t0(q[0],1,clk),
t1(q[1],1,q[0]),
t2(q[2],1,q[1]),
t3(q[3],1,q[2]);
endmodule

TFF:
module tff(q,qbar,t,clk);
output q,qbar;
input t,clk;
reg q = 0;
always @(posedge clk)
if(t)
q = ~q;
else
q = q;
assign qbar = ~q;
endmodule

Simulated Output:

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SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM.

Post Place and Route Simulated Output:

RTL Schematic:

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EC1404 - VLSI LAB MANUAL

Device utilization summary:

Selected Device

: 3s400tq144-4

Number of Slices

: 2 out of 2448

0%

Number of Slice Flip Flops : 4 out of 4896

0%

Number of 4 input LUTs

: 4 out of 4896

0%

Number of IOs

:5

Number of bonded IOBs

: 5 out of 158

Number of GCLKs

: 1out of

24

3%
4%

Timing Detail:

Timing constraint: Default period analysis for Clock 't2/q'

Clock period: 2.131ns (frequency: 469.274MHz)
Total number of paths / destination ports: 1 / 1
------------------------------------------------------------------------Delay:
Source:
Destination:
Source Clock:

2.131ns (Levels of Logic = 1)

t3/q (FF)
t3/q (FF)
t2/q rising

Destination Clock: t2/q rising

Data Path: t3/q to t3/q

Gate
Cell:in->out

Net

fanout Delay Delay Logical Name (Net Name)

---------------------------------------- -----------FDE:C->Q
INV:I->O
FDE:D
Total

2 0.514 0.380 t3/q (t3/q)

1 0.612 0.357 t3/qbar1_INV_0 (t3/qbar)
0.268

t3/q

2.131ns (1.394ns logic, 0.737ns route)

(65.4% logic, 34.6% route)

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UCF (User Constraints File):

NET clk LOC = p52 ;

NET "q[0]" LOC = "p84" ;
NET "q[1]" LOC = "p86" ;
NET "q[2]" LOC = "p87" ;
NET "q[3]" LOC = "p88" ;

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EC1404 - VLSI LAB MANUAL

Verilog Module:
module real_time_clk(clk,clear,hour1,hour2,minute1,minute2,second1, second2, hour_A2,
min_A1,sec_A0,load,data_in);
input clk,clear;
output reg [6:0]hour1,hour2,minute1,minute2,second1,second2;
input load; input hour_A2,min_A1,sec_A0;
input [7:0]data_in;
reg clk_sec,clk_msec;
reg [7:0]sec,min,hr;
integer timer_count1=0,timer_count2=0;
always@(posedge clk)
begin
if(timer_count1==3999)
begin
timer_count1=0; clk_msec=1'b1;
end
else
begin
timer_count1=timer_count1+1;
clk_msec=1'b0;
end
end
always@(posedge clk_msec)
begin
if(timer_count2==999)
begin
timer_count2=0;
clk_sec=1'b1;
end
else
begin
timer_count2=timer_count2+1;
clk_sec=1'b0;
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end
end
always@(negedge clk_sec)
begin
if(~clear)
begin
sec=0;
min=0;
hr=0;
end
else
if(~load)
begin
if(hour_A2)
begin
if(hr[7:4] == 4'b0010)
begin
if(hr[3:0] < 4'b0100)
hr = data_in;
end
else if(hr[7:4] < 4'b0010)
hr = data_in;
else
hr = 8'b0;
end
if(min_A1)
begin
if(min[7:4] < 4'b0110)
min = data_in;
else
min = 8'b0;
end
if(sec_A0)
begin
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if (sec[7:4] < 4'b0110)

sec = data_in;
else
sec = 8'b0;
end
end
else
begin
if(sec[3:0]==4'b1001)
begin sec[3:0]=4'b0;
if(sec[7:4]==4'b0101)
begin
sec[7:4]=4'b0;
if(min[3:0]==4'b1001)
begin
min[3:0]=4'b0;
if(min[7:4]==4'b0101)
begin
min[7:4]=4'b0;
if(hr==8'b00100100)
hr=0;
else if(hr[3:0]==4'b1001)
begin
hr[3:0]=4'b0;
hr[7:4]=hr[7:4]+1;
end
else
hr[3:0]=hr[3:0]+1; //hours count completed
end
else
min[7:4]=min[7:4]+1;
end
else
min[3:0]=min[3:0]+1; // minutes count completed
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end
else

sec[7:4]=sec[7:4]+1;

end
else
sec[3:0]=sec[3:0]+1; //seconds count completed
end
end
always@(sec)
begin
case (sec[3:0])
4'b0000: second1=7'b1111110;
4'b0001: second1=7'b0110000;
4'b0010: second1=7'b1101101;
4'b0011: second1=7'b1111001;
4'b0100: second1=7'b0110011;
4'b0101: second1=7'b1011011;
4'b0110: second1=7'b1011111;
4'b0111: second1=7'b1110000;
4'b1000: second1=7'b1111111;
4'b1001: second1=7'b1111011;
default: second1=7'b0;
endcase
end
always@(sec)
begin
case(sec[7:4])
4'b0000: second2=7'b1111110;
4'b0001: second2=7'b0110000;
4'b0010: second2=7'b1101101;
4'b0011: second2=7'b1111001;
4'b0100: second2=7'b0110011;
4'b0101: second2=7'b1011011;
4'b0110: second2=7'b1011111;
4'b0111: second2=7'b1110000;
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4'b1000: second2=7'b1111111;
4'b1001: second2=7'b1111011;
default: second2=7'b0;
endcase
end

always@(min)
begin
case(min[3:0])
4'b0000: minute1=7'b1111110;
4'b0001: minute1=7'b0110000;
4'b0010: minute1=7'b1101101;
4'b0011: minute1=7'b1111001;
4'b0100: minute1=7'b0110011;
4'b0101: minute1=7'b1011011;
4'b0110: minute1=7'b1011111;
4'b0111: minute1=7'b1110000;
4'b1000: minute1=7'b1111111;
4'b1001: minute1=7'b1111011;
default: minute1=7'b0;
endcase
end

always@(min)
begin
case(min[7:4])
4'b0000: minute2=7'b1111110;
4'b0001: minute2=7'b0110000;
4'b0010: minute2=7'b1101101;
4'b0011: minute2=7'b1111001;
4'b0100: minute2=7'b0110011;
4'b0101: minute2=7'b1011011;
4'b0110: minute2=7'b1011111;
4'b0111: minute2=7'b1110000;
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4'b1000: minute2=7'b1111111;
4'b1001: minute2=7'b1111011;
default: minute2=7'b0;
endcase
end

always@(hr)
begin
case(hr[3:0])
4'b0000: hour1=7'b1111110;
4'b0001: hour1=7'b0110000;
4'b0010: hour1=7'b1101101;
4'b0011: hour1=7'b1111001;
4'b0100: hour1=7'b0110011;
4'b0101: hour1=7'b1011011;
4'b0110: hour1=7'b1011111;
4'b0111: hour1=7'b1110000;
4'b1000: hour1=7'b1111111;
4'b1001: hour1=7'b1111011;
default: hour1=7'b0;
endcase
end

always@(hr)
begin
case(hr[7:4])
4'b0000: hour2=7'b1111110;
4'b0001: hour2=7'b0110000;
4'b0010: hour2=7'b1101101;
4'b0011: hour2=7'b1111001;
4'b0100: hour2=7'b0110011;
4'b0101: hour2=7'b1011011;
4'b0110: hour2=7'b1011111;
4'b0111: hour2=7'b1110000;
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4'b1000: hour2=7'b1111111;
4'b1001: hour2=7'b1111011;
default: hour2=7'b0;
endcase
end
endmodule

Simulated Output:

Post Place and Route Simulated Output:

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EC1404 - VLSI LAB MANUAL

SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM.

RTL Schematic:

Counter Section:

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Sub Section:

Sub Section:

Sub Section:

Device utilization summary:

Selected Device

: 3s400tq144-4

Number of Slices

: 58 out of 2448

2%

Number of Slice Flip Flops : 24 out of 4896

0%

Number of 4 input LUTs

: 110 out of 4896

Number of IOs

: 56

Number of bonded IOBs

: 56 out of 158 35%

Number of GCLKs

: 1 out of

24
80

4%

2%

EC1404 - VLSI LAB MANUAL

SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM.

EC1404 - VLSI LAB MANUAL

Timing Detail:

All values displayed in nanoseconds (ns)

Timing constraint: Default period analysis for Clock 'clk'
Clock period: 6.021ns (frequency: 166.074MHz)
Total number of paths / destination ports: 552 / 44
------------------------------------------------------------------------Delay:

6.021ns (Levels of Logic = 4)

Source:
Destination:

hr_3 (FF)
hr_6 (FF)

Source Clock:

clk falling

Destination Clock: clk falling

Data Path: hr_3 to hr_6
Gate
Cell:in->out

Net

fanout Delay Delay Logical Name (Net Name)

---------------------------------------- -----------FDRE_1:C->Q

11 0.514 0.945

hr_3 (hr_3)

LUT3:I0->O

2 0.612 0.383

hr_7_cmp_eq0001_SW0_SW0 (N375)

LUT4:I3->O

8 0.612 0.646

hr_7_cmp_eq0001 (hr_7_cmp_eq0001)

LUT4_L:I3->LO 1 0.612 0.103

hr_7_not000120_SW0 (N393)

LUT4:I3->O

4 0.612 0.499

hr_7_not000120 (hr_7_not0001)

FDRE_1:CE

0.483

hr_6

---------------------------------------Total

6.021ns (3.445ns logic, 2.576ns route) (57.2% logic, 42.8% route)

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User Constraints File (UCF):

NET clk LOC = p52;

NET clear LOC = p137;
NET data_in<0> LOC = p92;
NET data_in<1> LOC = p96;
NET data_in<2> LOC = p74;
NET data_in<3> LOC = p76;
NET data_in<4> LOC = p77;
NET data_in<5> LOC = p79;
NET data_in<6> LOC = p84;
NET data_in<7> LOC = p85;
NET hour1<0> LOC = p95;
NET hour1<1> LOC = p97;
NET hour1<2> LOC = p98;
NET hour1<3> LOC = p99;
NET hour1<4> LOC = p104;
NET hour1<5> LOC = p125;
NET hour1<6> LOC = p122;
NET hour2<0> LOC = p112;
NET hour2<1> LOC = p116;
NET hour2<2> LOC = p119;
NET hour2<3> LOC = p118;
NET hour2<4> LOC = p123;
NET hour2<5> LOC = p131;
NET hour2<6> LOC = p93;
NET hour_A2 LOC = p78;
NET load LOC = p83;
NET min_A1 LOC = p82;
NET minute1<0> LOC = p14;
NET minute1<1> LOC = p15;
NET minute1<2> LOC = p17;
NET minute1<3> LOC = p18;
NET minute1<4> LOC = p21;
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NET minute1<5> LOC = p23;

NET minute1<6> LOC = p24;
NET minute2<0> LOC = p129;
NET minute2<1> LOC = p132;
NET minute2<2> LOC = p135;
NET minute2<3> LOC = p140;
NET minute2<4> LOC = p1;
NET minute2<5> LOC = p12;
NET minute2<6> LOC = p13;
NET sec_A0 LOC = p80;
NET second1<0> LOC = p32;
NET second1<1> LOC = p35;
NET second1<2> LOC = p36;
NET second1<3> LOC = p40;
NET second1<4> LOC = p41;
NET second1<5> LOC = p56;
NET second1<6> LOC = p60;
NET second2<0> LOC = p26;
NET second2<1> LOC = p27;
NET second2<2> LOC = p6;
NET second2<3> LOC = p7;
NET second2<4> LOC = p8;
NET second2<5> LOC = p11;
NET second2<6> LOC = p10;

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EC1404 - VLSI LAB MANUAL

Verilog Module:
module traffic_verilog(seg_1,seg_2,R1,R2,R3,G1,G2,G3,Y1,Y2,Y3,PR,PG,clk,rst);
output reg R1,R2,R3,G1,G2,G3,Y1,Y2,Y3,PR,PG;
output reg [6:0]seg_1,seg_2;
input clk,rst;
integer timer_count1 = 0,timer_count2 = 0;
reg clk_msec,clk_sec;
reg [7:0]count;
reg [1:0]state = 2'b0;
always@(posedge clk)
begin
if(timer_count1==3999)
begin
timer_count1=0;
clk_msec=1'b1;
end
else
begin
timer_count1=timer_count1+1;
clk_msec=1'b0;
end
end
always@(posedge clk_msec)
begin
if(timer_count2==999)
begin
timer_count2=0;
clk_sec=1'b1;
end
else
begin
timer_count2=timer_count2+1;
clk_sec=1'b0;
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end
end

always@(posedge clk_sec)
begin
if(~rst)
begin
R1 = 1'b1; G1 = 1'b0; Y1 = 1'b0;
R2 = 1'b1; G2 = 1'b0; Y2 = 1'b0;
R3 = 1'b1; G3 = 1'b0; Y3 = 1'b0;
state=2'b00;
end
else
begin
case(state)
2'b00://SIGNAL AT SIGNAL LIGHTS ONE
begin
if(count==8'b00100101)
begin
R1 = 1'b0; G1 = 1'b1; Y1 = 1'b0;
end
if(count==8'b00101001)
begin
G1 = 1'b1; Y1 = 1'b0;
state=2'b01;
end
else
state=2'b00;
end

2'b01://SIGNAL AT SIGNAL LIGHTS TWO

begin
if(count==8'b00100101)
begin
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EC1404 - VLSI LAB MANUAL

Y1 = 1'b1; G1 = 1'b0;R2 = 1'b0; Y2 = 1'b1; G2 = 1'b0;

end
if(count==8'b00101001)
begin
R1 = 1'b1; Y1 = 1'b0; Y2 = 1'b0; G2 = 1'b1;
state = 2'b10;
end
else
state=2'b01;
end

2'b10://SIGNAL AT SIGNAL LIGHTS THREE

begin
if(count==8'b00100101)
begin
Y2 = 1'b1; G2 = 1'b0; R3 = 1'b0; Y3 = 1'b1; G3 = 1'b0;
end
if(count==8'b00101001)
begin
R2 = 1'b1; Y2 = 1'b0; Y3 = 1'b0; G3 = 1'b1;
state = 2'b11;
end
else state=2'b10; end
2'b11://ALL SIGNAL HIGH TO ALLOW PEDESTRIALS TO CROSS
begin
if(count==8'b00100101)
begin
Y3 = 1'b1; G3 = 1'b0;
end
if(count==8'b00101001)
begin
R3 = 1'b1; Y3 = 1'b0;
state = 2'b00;
end
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else
state=2'b11;
end
endcase
end
end

always@ (count, state)

begin
if((state==2'b00)&&(count==8'b00101001))
begin
PR = 1'b1;
PG = 1'b0;
end
else
begin
PR = 1'b0; PG = 1'b1;
end
end
always@(posedge clk_sec)
begin
if(rst==1'b0)
count=8'b00000000;
else if(clk_sec)
begin
if(count[3:0]==4'b1001)
begin
count[3:0]=4'b0000;
if(count[7:4]==4'b0010)
count[7:4]=4'b0000;
else
count[7:4]=count[7:4]+1;
end
else
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count[3:0]=count[3:0]+1;
end
end

always@(count)
begin
case(count[3:0])
4'b0000:seg_1 = 8'b1111110; //0
4'b0001:seg_1 = 8'b0110000; //1
4'b0010:seg_1 = 8'b1101101; //2
4'b0011:seg_1 = 8'b1111001; //3
4'b0100:seg_1 = 8'b0110011; //4
4'b0101:seg_1 = 8'b1011011; //5
4'b0110:seg_1 = 8'b1011111; //6
4'b0111:seg_1 = 8'b1110000; //7
4'b1000:seg_1 = 8'b1111111; //8
4'b1001:seg_1 = 8'b1111011; //9
default:seg_1 = 8'b0000000; //off
endcase
case(count[7:4])
4'b0000:seg_2 = 8'b1111110; //0
4'b0001:seg_2 = 8'b0110000; //1
4'b0010:seg_2 = 8'b1101101; //2
4'b0011:seg_2 = 8'b1111001; //3
4'b0100:seg_2 = 8'b0110011; //4
4'b0101:seg_2 = 8'b1011011; //5
4'b0110:seg_2 = 8'b1011111; //6
4'b0111:seg_2 = 8'b1110000; //7
4'b1000:seg_2 = 8'b1111111; //8
4'b1001:seg_2 = 8'b1111011; //9
default:seg_2 = 8'b0000000; //off
endcase
end
endmodule
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RTL Schematic:

Simulated Output:

89

EC1404 - VLSI LAB MANUAL

SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM.

Device Utilization Summary:

Selected Device

: 3s400tq144-4

Number of Slices

: 71 out of 3584

1%

Number of Slice Flip Flops : 85 out of 7168

1%

Number of 4 input LUTs

: 138 out of 7168

Number of IOs

: 27

Number of bonded IOBs

: 27 out of

97 27%

Number of GCLKs

: 2 out of

8 25%

UCF File (User Constraints file):

NET clk LOC = p52;
NET G1 LOC = p97;
NET G2 LOC = p98;
NET G3 LOC = p125;
NET PG LOC = p132;
NET PR LOC = p135;
NET R1 LOC = p93;
NET R2 LOC = p104;
NET R3 LOC = p129;
NET rst LOC = p78;
NET seg_1<6> LOC = p27;
NET seg_1<5> LOC = p26;
NET seg_1<4> LOC = p24;
NET seg_1<3> LOC = p23;
NET seg_1<2> LOC = p21;
NET seg_1<1> LOC = p18;
NET seg_1<0> LOC = p17;
NET seg_1<6> LOC = p15;
NET seg_1<5> LOC = p14;
NET seg_1<4> LOC = p13;
NET seg_1<3> LOC = p12;
NET seg_1<2> LOC = p1;
NET seg_1<1> LOC = p83;
90

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NET seg_1<0> LOC = p80;

NET Y1 LOC = p95;
NET Y2 LOC = p99;
NET Y3 LOC = p122;

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EC1404 - VLSI LAB MANUAL

Verilog Module:
module serial_AS_verilog(clk,addr,load,clear,data_in,calc,result);
input clk,clear,calc,load;
input [3:0]addr;
input [11:0]data_in;
output reg [11:0]result;
reg [11:0]ram[7:0];
reg [11:0]temp;
reg [2:0]count = 3'b000;
always@(negedge clk)
begin
if(clk)
case(count)
3'b000: begin
temp = ram[0] + ram[1];
count = count + 1'b1;
end
3'b001: begin
temp = (temp + ram[2]);
count = 3'b010;
end
3'b010: begin
temp = (temp + ram[3]);
count = 3'b011;
end
3'b011: begin
temp = (temp + ram[4]);
count = 3'b100;
end
3'b100: begin
temp = (temp + ram[5]);
count = 3'b101;
end
3'b101: begin
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temp = (temp + ram[6]);

count = 3'b110;
end
default: begin
temp = (temp + ram[7]);
count = 3'b000;
end
endcase
end
always@(posedge clk)
begin if(~clear)
begin
ram[0]=12'b0;
ram[1]=12'b0;
ram[2]=12'b0;
ram[3]=12'b0;
ram[4]=12'b0;
ram[5]=12'b0;
ram[6]=12'b0;
ram[7]=12'b0;
end
else if(~load)
begin
result=data_in;
ram[addr] = data_in;
end
else if(~calc)
result = temp;
else
result = ram[addr];
end
endmodule

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EC1404 - VLSI LAB MANUAL

Procedure:
Download the programme into FPGA kit and connect the FRC connectors as specified. On
card1 load the 12bit numbers by using the switches SW0 to SW11 and selection of 8
numbers are made one by one by selecting lines assigned A0, A1,\, A2 and after selecting
each 12 bit number by pressing the LOAD switch you can enter the values. For each
locations of 8 numbers and after loading all values keep pressing CALC switch the result
can be verified by LEDs on board.

Device utilization summary:

Selected Device

: 3s400tq144-4

Number of Slices

: 123 out of 3584

3%

Number of Slice Flip Flops : 123 out of 7168

1%

Number of 4 input LUTs

: 157 out of 7168

2%

Number of IOs

: 32

Number of bonded IOBs

: 31 out of

97 31%

Number of GCLKs

: 1 out of

8 12%

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EC1404 - VLSI LAB MANUAL

RTL SCHEMATIC:

Timing Detail:
All values displayed in nanoseconds (ns)
Timing constraint: Default period analysis for Clock 'clk'
Clock period: 15.412ns (frequency: 64.884MHz)
Total number of paths / destination ports: 2801 / 27
------------------------------------------------------------------------Delay:

7.706ns (Levels of Logic = 16)

Source:
Destination:
Source Clock:

ram_2_0 (FF)
temp_11 (FF)
clk rising

Destination Clock: clk falling

Data Path: ram_2_0 to temp_11
Gate
Cell:in->out

Net

fanout Delay Delay Logical Name (Net Name)

---------------------------------------- -----------FDRE:C->Q

2 0.720 1.072 ram_2_0 (ram_2_0)

LUT3:I1->O

1 0.551 0.000 temp_mux0001<0>131_F (N1021)

95

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MUXF5:I0->O

EC1404 - VLSI LAB MANUAL

1 0.360 0.827 temp_mux0001<0>131

(temp_mux0001<0>1_map11)
LUT4:I3->O

1 0.551 0.827 temp_mux0001<0>1118 (temp_mux0001<0>)

LUT4:I3->O

2 0.551 0.000 Madd_temp_mux0000_lut<0> (N5)

MUXCY:S->O

1 0.500 0.000 Madd_temp_mux0000_cy<0>

(Madd_temp_mux0000_cy<0>)
MUXCY:CI->O

1 0.064 0.000 Madd_temp_mux0000_cy<1>

(Madd_temp_mux0000_cy<1>)
MUXCY:CI->O

1 0.064 0.000 Madd_temp_mux0000_cy<2>

(Madd_temp_mux0000_cy<2>)
MUXCY:CI->O

1 0.064 0.000 Madd_temp_mux0000_cy<3>

(Madd_temp_mux0000_cy<3>)
MUXCY:CI->O

1 0.064 0.000 Madd_temp_mux0000_cy<4>

(Madd_temp_mux0000_cy<4>)
MUXCY:CI->O

1 0.064 0.000 Madd_temp_mux0000_cy<5>

(Madd_temp_mux0000_cy<5>)
MUXCY:CI->O

1 0.064 0.000 Madd_temp_mux0000_cy<6>

(Madd_temp_mux0000_cy<6>)
MUXCY:CI->O

1 0.064 0.000 Madd_temp_mux0000_cy<7>

(Madd_temp_mux0000_cy<7>)
MUXCY:CI->O

1 0.064 0.000 Madd_temp_mux0000_cy<8>

(Madd_temp_mux0000_cy<8>)
MUXCY:CI->O

1 0.064 0.000 Madd_temp_mux0000_cy<9>

(Madd_temp_mux0000_cy<9>)
MUXCY:CI->O

0 0.064 0.000 Madd_temp_mux0000_cy<10>

(Madd_temp_mux0000_cy<10>)
XORCY:CI->O

1 0.904 0.000 Madd_temp_mux0000_xor<11>

(temp_mux0000<11>)
FDE_1:D

0.203

temp_11

---------------------------------------Total

7.706ns (4.980ns logic, 2.726ns route)

(64.6% logic, 35.4% route)

96

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EC1404 - VLSI LAB MANUAL

Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'

Total number of paths / destination ports: 815 / 327
------------------------------------------------------------------------Offset:

6.463ns (Levels of Logic = 6)

Source:

addr<0> (PAD)

Destination:

result_4 (FF)

Destination Clock: clk rising

Data Path: addr<0> to result_4
Gate
Cell:in->out

Net

fanout Delay Delay Logical Name (Net Name)

---------------------------------------- -----------IBUF:I->O

56 0.821 2.330 addr_0_IBUF (addr_0_IBUF)

LUT3:I0->O

1 0.551 0.000 mux1_4 (N22)

MUXF5:I1->O

1 0.360 0.000 mux1_3_f5 (mux1_3_f5)

MUXF6:I1->O

2 0.342 0.945 mux1_2_f6 (_COND_1<10>)

LUT4:I2->O

1 0.551 0.000 result_mux0000<10>_F (N1059)

MUXF5:I0->O
FDE:D
Total

1 0.360 0.000 result_mux0000<10> (result_mux0000<10>)

0.203

result_10

6.463ns (3.188ns logic, 3.275ns route) (49.3% logic, 50.7% route)

================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Total number of paths / destination ports: 12 / 12
Offset:
Source:
Destination:
Source Clock:

7.165ns (Levels of Logic = 1)

result_11 (FF)
result<11> (PAD)
clk rising

Data Path: result_11 to result<11>

Gate
Cell:in->out

Net

fanout Delay Delay Logical Name (Net Name)

---------------------------------------- -----------FDE:C->Q
OBUF:I->O

1 0.720 0.801 result_11 (result_11)

5.644

result_11_OBUF (result<11>)

---------------------------------------Total

7.165ns (6.364ns logic, 0.801ns route) (88.8% logic, 11.2% route)

97

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User Constraints File:

NET addr<0> LOC = p80;
NET addr<1> LOC = p82;
NET addr<2> LOC = p78;
NET calc LOC = p130;
NET clear LOC = p137;
NET clk LOC = p52;
NET data_in<0> LOC = p92;
NET data_in<1> LOC = p89;
NET data_in<2> LOC = p90;
NET data_in<3> LOC = p96;
NET data_in<4> LOC = p74;
NET data_in<5> LOC = p76;
NET data_in<6> LOC = p77;
NET data_in<7> LOC = p79;
NET data_in<8> LOC = p84;
NET data_in<9> LOC = p85;
NET load LOC = p83;
NET result<7> LOC = p28;
NET result<6> LOC = p63;
NET result<5> LOC = p69;
NET result<4> LOC = p31;
NET result<3> LOC = p33;
NET result<2> LOC = p44;
NET result<1> LOC = p46;
NET result<0> LOC = p47;
NET result<8> LOC = p50;
NET result<9> LOC = p51;
NET result<10> LOC = p57;
NET result<11> LOC = p59;

98

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SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM.

EC1404 - VLSI LAB MANUAL

Connections:
1. Connect FRC 1 of main board connector to CN8 of Card1.
2. Connect FRC 2 of main board connector to CN7 of Card1.
3. Connect FRC 7 of main board connector to CN6 of Card1.
4. Connect FRC 6 of main board connector to CN5 of Card1.
5. Connect FRC 4 of main board connector to CN4 of Card1.
6. Connect FRC 5 of main board connector to CN1 of Card1.

Verilog Code:
module parallel (clk, addr, load, clear, data_in, calc, result);
input clk, clear, calc, load;
input [2:0] addr;
input [11:0] data_in;
output reg[11:0] result;
reg [11:0]ram[7:0];
wire[11:0] temp;

always@(posedge clk)
begin
if(~clear)
begin
ram[0]=12b0;
ram[1]=12b0;
ram[2]=12b0;
ram[3]=12b0;
ram[4]=12b0;
ram[5]=12b0;
ram[6]=12b0;
ram[7]=12b0;
end
else if(!load)
ram[addr] =data_in;
end
99

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EC1404 - VLSI LAB MANUAL

assign temp = ram[0] + ram[1] + ram[2] + ram[3] + ram[4] + ram[5] + ram[6] + ram[7];
always@(posedge clk)
begin
if(~load)
result = data_in;
else if(~calc)
result=temp;
else
result=ram[addr];
end
endmodule

Simulated Output:

100

SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM.

Post Place and Route Output:

RTL Schematic:

101

EC1404 - VLSI LAB MANUAL

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EC1404 - VLSI LAB MANUAL

Device utilization summary:

Selected Device

: 3s400tq144-4

Number of Slices

: 115 out of 3584

3%

Number of Slice Flip Flops : 108 out of 7168

1%

Number of 4 input LUTs

: 202 out of 7168

2%

Number of IOs

: 31

Number of bonded IOBs

: 31 out of

97 31%

Number of GCLKs

: 1 out of

8 12%

Clock Information:
Clock Signal

| Clock buffer (FF name) | Load |

clk

| BUFGP

|108 |

Timing Detail:
Delay:

16.703ns (Levels of Logic = 17)

Source:
Destination:

ram_1_1 (FF)
result_11 (FF)

Source Clock:

clk rising

Destination Clock: clk rising

Data Path: ram_1_1 to result_11
Gate
Cell:in->out

Net

fanout Delay Delay Logical Name (Net Name)

---------------------------------------- -----------FDRE:C->Q

3 0.720 1.246 ram_1_1 (ram_1_1)

LUT3:I0->O

1 0.551 0.827 Madd_temp_addsub0001C1

(Madd_temp_addsub0001C)
LUT4:I3->O
MUXCY:S->O

1 0.551 0.000 Madd_temp_addsub0001_Madd_lut<2> (N9)

1 0.500 0.000 Madd_temp_addsub0001_Madd_cy<2>

(Madd_temp_addsub0001_Madd_cy<2>)
MUXCY:CI->O

1 0.064 0.000 Madd_temp_addsub0001_Madd_cy<3>

(Madd_temp_addsub0001_Madd_cy<3>)
MUXCY:CI->O

1 0.064 0.000 Madd_temp_addsub0001_Madd_cy<4>

(Madd_temp_addsub0001_Madd_cy<4>)
102

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MUXCY:CI->O

EC1404 - VLSI LAB MANUAL

1 0.064 0.000 Madd_temp_addsub0001_Madd_cy<5>

(Madd_temp_addsub0001_Madd_cy<5>)
XORCY:CI->O

3 0.904 0.975 Madd_temp_addsub0001_Madd_xor<6>

(temp_addsub0001<6>)
LUT3:I2->O

0 0.551 0.000 Madd_temp_addsub0003C51

(Madd_temp_addsub0003C5)
MUXCY:DI->O

1 0.889 0.000 Madd_temp_addsub0003_Madd_cy<7>

(Madd_temp_addsub0003_Madd_cy<7>)
XORCY:CI->O

3 0.904 0.975 Madd_temp_addsub0003_Madd_xor<8>

(temp_addsub0003<8>)
LUT3:I2->O

0 0.551 0.000 Madd_temp_addsub0005C71

(Madd_temp_addsub0005C7)
MUXCY:DI->O

1 0.889 0.000 Madd_temp_addsub0005_Madd_cy<9>

(Madd_temp_addsub0005_Madd_cy<9>)
XORCY:CI->O

1 0.904 0.996 Madd_temp_addsub0005_Madd_xor<10>

(temp_addsub0005<10>)
LUT2:I1->O

1 0.551 0.000 Madd_temp_lut<10> (N513)

MUXCY:S->O

0 0.500 0.000 Madd_temp_cy<10> (Madd_temp_cy<10>)

XORCY:CI->O

1 0.904 0.869 Madd_temp_xor<11> (temp<11>)

LUT3:I2->O
FD:D

1 0.551 0.000 result_mux0000<11> (result_mux0000<11>)

0.203

result_11

---------------------------------------Total

16.703ns (10.815ns logic, 5.888ns route)

(64.7% logic, 35.3% route)

================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Total number of paths / destination ports: 806 / 300
------------------------------------------------------------------------Offset:
Source:
Destination:

7.752ns (Levels of Logic = 6)

addr<0> (PAD)
result_3 (FF)

Destination Clock: clk rising

Data Path: addr<0> to result_3

103

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Gate
Cell:in->out

EC1404 - VLSI LAB MANUAL

Net

fanout Delay Delay Logical Name (Net Name)

---------------------------------------- -----------IBUF:I->O

56 0.821 2.330 addr_0_IBUF (addr_0_IBUF)

LUT3:I0->O

1 0.551 0.000 mux1_4 (N22)

MUXF5:I1->O

1 0.360 0.000 mux1_3_f5 (mux1_3_f5)

MUXF6:I1->O

2 0.342 0.903 mux1_2_f6 (_varindex0000<10>)

LUT4:I3->O

1 0.551 1.140 result_mux0000<10>_SW1 (N162)

LUT3:I0->O

1 0.551 0.000 result_mux0000<10> (result_mux0000<10>)

FD:D

0.203

result_10

---------------------------------------Total

7.752ns (3.379ns logic, 4.373ns route)

(43.6% logic, 56.4% route)

================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Total number of paths / destination ports: 12 / 12
------------------------------------------------------------------------Offset:
Source:
Destination:
Source Clock:

7.165ns (Levels of Logic = 1)

result_11 (FF)
result<11> (PAD)
clk rising

Data Path: result_11 to result<11>

Gate
Cell:in->out

Net

fanout Delay Delay Logical Name (Net Name)

---------------------------------------- -----------FD:C->Q
OBUF:I->O

1 0.720 0.801 result_11 (result_11)

5.644

result_11_OBUF (result<11>)

---------------------------------------Total

7.165ns (6.364ns logic, 0.801ns route)

(88.8% logic, 11.2% route)

104

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Verilog Module:
module buffer(a, y);
input [0:7] a;
output [0:7] y;
reg[7:0] y;
always@(a)
begin
y = a;
end
endmodule

Simulated Output:

105

EC1404 - VLSI LAB MANUAL

SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM.

Post Place and Route Output:

RTL Schematic:

Device utilization summary:

Selected Device

: 3s400tq144-4

Number of Slices

: 0 out of 3584

Number of IOs

: 16

Number of bonded IOBs

: 16 out of

0%

97 16%

106

EC1404 - VLSI LAB MANUAL

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EC1404 - VLSI LAB MANUAL

Timing Detail:

Timing constraint: Default path analysis

Total number of paths / destination ports: 8 / 8
------------------------------------------------------------------------Delay:
Source:
Destination:

7.266ns (Levels of Logic = 2)

a<0> (PAD)
y<7> (PAD)

Data Path: a<0> to y<7>

Gate
Cell:in->out

Net

fanout Delay Delay Logical Name (Net Name)

---------------------------------------- -----------IBUF:I->O

1 0.821 0.801 a_0_IBUF (y_7_OBUF)

OBUF:I->O

5.644 y_7_OBUF (y<7>)

---------------------------------------Total

7.266ns (6.465ns logic, 0.801ns route)

(89.0% logic, 11.0% route)

User Constraints File (UCF):

NET a<0> LOC = p83;

NET a<1> LOC = p80;
NET a<2> LOC = p82;
NET a<3> LOC = p78;
NET a<4> LOC = p79;
NET a<5> LOC = p77;
NET a<6> LOC = p76;
NET a<7> LOC = p74;
NET y<0> LOC = p96;
NET y<1> LOC = p92;
NET y<2> LOC = p92;
NET y<3> LOC = p89;
NET y<4> LOC = p87;
107

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NET y<5> LOC = p86;

NET y<6> LOC = p85;
NET y<7> LOC = p84;

108

EC1404 - VLSI LAB MANUAL