OR AND LOGIC GATE

LAB 2 ECE 195

Menchie O. Labadan BSE ECE V

OR AND SPECIFICATIONS Wp Lp mp Wn Ln mn 12 0.8 1 8 0.8 1

OR AND LOGIC GATE LAYOUT

Schematic

Symbol

INVERTER LAYOUT SCHEMATIC

SYMBOL

NOR

LAYOUT

SCHEMATIC

SYMBOL

NAND

LAYOUT

SCHEMATIC

SYMBOL

OR

LAYOUT

SCHEMATIC

SYMBOL

AND

LAYOUT

SCHEMATIC

SYMBOL

DRC

LVS

LPE

Testbench

Truth Table for Or And Logic Gate

Y 0 0 0 0 1 1 1 1

INPUTS X 0 0 1 1 0 0 1 1

OR Z 0 1 0 1 0 1 0 1
(Y or X)

OUTPUT
(X or Y) and Z 0 0 0 1 0 1 0 1

0 0 1 1 1 1 1 1

PreSimulation

Post Simulation

Comparing Postsim and Presim