DIGITAL LOGIC AND

COMPUTER ORGANIZATION
Lecture 3: Logic gates
ELEC3010
ACKNOWLEGEMENT

I would like to express my special thanks to Professor Zhiru Zhang

School of Electrical and Computer Engineering, Cornell University
and Prof. Rudy Lauwereins, KU Leuven for sharing their teaching
materials.

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COVERED IN THIS COURSE
❑ Binary numbers and logic gates
❑ Boolean algebra and combinational logic
❑ Sequential logic and state machines
❑ Binary arithmetic
Digital logic
❑ Memories

❑ Instruction set architecture

❑ Processor organization Computer
❑ Caches and virtual memory
❑ Input/output Organization
❑ Advanced topics
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MOTIVATION EXAMPLE

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 TRANSISTORS
Source Gate Drain Source Gate Drain
—
Insulator Insulator
- + + + + + + + + - - + + + + -
+ + channel created
+ + P-type
- + + + - - - + + + - - + + + - +- - + ++ -
P-type - P-type P-type - P-type
- N-type - - N-type
- - - - - - - - -
- - - - - - - - - - - -
- - - - - - - - - - - - - -

Off On
N-Type Silicon: negative free-carriers (electrons)
P-Type Silicon: positive free-carriers (holes)
P-Transistor: neg. charge on gate generates electric field that creates a (+ charged) p-channel connecting source & drain
N-Transistor: works the opposite way
Metal-Oxide Semiconductor (Gate-Insulator-Silicon)
Complementary MOS = CMOS technology uses both p- & n-type transistors

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 CMOS NOTATION
Off/Open On/Closed
N-type
0 1
gate

P-type
Off/Open On/Closed

1 0

Gate input controls whether current can flow between the other two
terminals or not.

Hint: the “o” bubble of the p-type tells you that this gate wants a 0 to be
turned on
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 2-TRANSISTOR COMBINATION: NOT
• Logic gates are constructed by combining transistors in complementary arrangements
• Combine p&n transistors to make a NOT gate:

CMOS Inverter :
power source (1) power source (1) power source (1)

p-gate — p-gate + p-gate

closes stays open
input output 0 1 1 0
n-gate
n-gate n-gate
— + closes
stays open

ground (0) ground (0) ground (0)

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 INVERTER
Function: NOT
Vsupply (aka logic 1)
Symbol:

in out
in out

Truth Table: In Out

(ground is logic 0) 0 1
1 0
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 LOGIC GATES
• Digital circuit that either allows signal
to pass through it or not
• Used to build logic functions
• Seven basic logic gates:
NOT
AND,
George Boole,(1815-1864)
OR,
XOR, Did you know?
NAND (not AND), George Boole Inventor of the idea of logic
NOR (not OR), gates. He was born in Lincoln, England and
XNOR (not XOR) he was the son of a shoemaker.
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LOGIC GATES: NAMES, SYMBOLS, TRUTH TABLES

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 LOGIC SYMBOLS & NOTATION
NOT: = ā = !a = a NAND:
(a ⚫ b) = !(a & b) =  (a  b)
AND: = a ∙ b = a & b = a  b
NOR:
OR: =a+b =a|b =ab (a + b) = !(a | b) =  (a  b)
XNOR:
XOR: = a  b = ab+ āb (a ⨁ b) = ab + ab

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 NOR GATE
Vsupply Function: NOR
Symbol: a
A b
out

B
A B out
out
0 0 1
A B Truth Table:
0 1 0
Note: the 2 As are the same input. Technically there 1 0 0
should be only a single letter A, but it makes the
diagram messy. 1 1 0
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 CAN YOU DO IT?

Vsupply Vsupply
Truth Table: Which Gate
A B
out is this?
A B out
0 0 B (A) NOT
(B) OR
0 1 A (C) XOR
1 0 (D) AND
(E) NAND
1 1
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 CAN YOU DO IT?

Vsupply Vsupply
Truth Table: Which Gate
A B
out is this?
A B out
0 0 1 B (A) NOT
(B) OR
0 1 1 A (C) XOR
1 0 1 (D) AND
(E) NAND
1 1 0
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 CAN YOU DO IT?
a
b Which Gate
Out is this?
(A) NOT
A B out (B) OR
0 0 (C) XOR
Truth Table: (D) AND
0 1 (E) NAND
1 0
1 1
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 CAN YOU DO IT?
a
b Which Gate
Out is this?
(A) NOT
A B out (B) OR
0 0 0 (C) XOR
Truth Table: (D) AND
0 1 1 (E) NAND
1 0 1
1 1 0
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 UNIVERSAL GATES
NAND and NOR:
• Can implement any function with NAND or just NOR gates
• useful for manufacturing

• NOT: a

a
• AND:
b

• OR: a
b
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 NON-FUNCTIONAL PROPERTIES
❑ Logic voltage levels and noise margin
Driver Receiver NMH = VOH – VIH
NML = VIL-VOL
Vcc Vcc
VDD
Logic High
Output Range High Logic High
High
VOH NMH Input Range
VIH

VIL
VOL NML
Logic Low Low Logic Low
Low Input Range
Output Range
GND Input
Output
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 NON-FUNCTIONAL PROPERTIES
❑ Logic voltage levels and noise margin
Logic Family VDD VIL VIH VOL VOH
TTL 5 0.8 2.0 0.4 2.4
CMOS 5 1.35 3.15 0.33 3.84
LVTTL 3.3 0.8 2.0 0.4 2.4
LVCMOS 3.3 0.9 1.8 0.36 2.7

NMH = ?
NML = ?

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NON-FUNCTIONAL PROPERTIES
❑ Power Consumption
1
▪ Pdynamic = .C.f.V2DD
2
➢ C: proportional to chip area (trend: increase)
➢ f: trend: steep increase: 1MHz -> 4 GHz
➢ V: trend: steady decrease: 5 -> 3.3 -> 2.5 -> 1.8 -> 1.5 -> 1.2 ->
0.9
▪ Pstatic = IDDVDD
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 NON-FUNCTIONAL PROPERTIES
❑ Propagation delay

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 IMPLEMENTATION TECHNOLOGIES

❑ SSI, MSI, LSI, VLSI

❑ Custom design, Standard cell design, Gate array
❑ PLA, PLD, FPGA

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 IMPLEMENTATION TECHNOLOGIES
❑ SSI, MSI, LSI, VLSI
▪ SSI: Small Scale Integration
➢ < 10 gates per package
➢ gates directly connected to package pins
➢ designed using transistor level design
▪ MSI: Medium Scale Integration
➢ 10 - 100 gates per package
➢ registers, adders, parity generators, …
➢ designed using gate level design

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 IMPLEMENTATION TECHNOLOGIES
❑ SSI, MSI, LSI, VLSI
▪ LSI: Large Scale Integration
➢ 100 - 10K gates per package
➢ controllers, data paths
➢ designed using RTL design
▪ VLSI:Very Large Scale Integration
➢ 10K - 1M gates per package
➢ memory, microprocessor, microcontroller
➢ designed using behavioral level design

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 IMPLEMENTATION TECHNOLOGIES

❑ Custom design, Standard cell design, Gate array

❑ Custom design:
➢ Each transistor and each connection is designed individually as a
set of rectangles.
➢ Excellent for optimal design of library elements that are re-used
multiple times
➢ Companies design and sell such optimized libraries
➢ Has to be completely re-done each time technology changes
(every 18 months!)

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 IMPLEMENTATION TECHNOLOGIES

❑ Custom design, Standard cell design, Gate array

❑ Standard cell design:
➢ Cells are basic logic gates and elements
➢ Needs many masks in the fabrication process to connect cells
➢ Faster design time than custom design but less optimized in
terms of area and performance

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 IMPLEMENTATION TECHNOLOGIES

❑ Custom design, Standard cell design, Gate array

❑ Gate array:
➢ Two-dimensional grid of identical gates (e.g., NAND only, NOR
only)
➢ Needs one mask in the fabrication process to connect gates
➢ Faster design time and cheaper than standard cell design but
less optimized in terms of area and performance

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 IMPLEMENTATION TECHNOLOGIES

❑ PLA, PLD, FPGA:

▪ Programmable devices
▪ FPGA: Field Programmable Gate Array (SRAM based)
➢ FPGA chips are pre-fabricated
➢ Designers use CAD tools to design and program the
chips.

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IMPLEMENTATION TECHNOLOGIES

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 BEFORE NEXT CLASS

• Textbook: 2.5-2.8

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