DIGITAL LOGIC AND

COMPUTER ORGANIZATION
Lecture 19: Pipelined Microprocessor (P3)
ELEC3010
ACKNOWLEGEMENT

I would like to express my special thanks to Professor Zhiru Zhang

School of Electrical and Computer Engineering, Cornell University
and Prof. Rudy Lauwereins, KU Leuven for sharing their teaching
materials.

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COVERED IN THIS COURSE
❑ Binary numbers and logic gates
❑ Boolean algebra and combinational logic
❑ Sequential logic and state machines
❑ Binary arithmetic
Digital logic
❑ Memories

❑ Instruction set architecture

❑ Processor organization Computer
❑ Caches and virtual memory
❑ Input/output Organization
❑ Advanced topics
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PIPELINE CONTROL UNIT (CU)

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 PIPELINE CONTROL REQUIREMENTS
❑ Generate control signals for each stage
▪ IF: PCJ
▪ EX: MB, F
▪ MEM: MW, MD
▪ WB: LD
❑ Detect forwarding conditions and generate MUX control
signals
❑ Detect data hazards and insert pipeline bubbles
▪ Assumes no load delay slot defined in ISA
❑ Assume branch delay slot defined in ISA
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GENERATING CONTROL FOR EACH STAGE

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FORWARDING UNIT (PARTIAL)

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R-TYPE TO R-TYPE FORWARDING

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ANOTHER EXAMPLE: R-TYPE TO R-TYPE FORWARDING

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 R-TYPE TO R-TYPE FORWARDING CONDITIONS

❑ MEM➞EX
▪ MEM.DR == (EX.SA || EX.SB)

❑ WB➞EX
▪ WB.DR == (EX.SA || EX.SB) and
▪ MEM.DR != (EX.SA || EX.SB)

❑ WB➞ID
▪ WB.DR == (ID.SA || ID.SB)
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R-TYPE TO BRANCH FORWARDING

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PIPELINE WITH FWDING + BRANCH HW IN ID

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 DATA HAZARDS REQUIRING BUBBLES

❑ Occur when instructions are too close together for

forwarding to work
❑ Requires adding bubbles in the pipeline
❑ Data hazard conditions to detect and handle
▪ Load followed by R-type
▪ Load followed by I-type ALU instruction
▪ Load followed by Load
▪ Load followed by Store
▪ Load followed by Branch
▪ ALU instruction followed by Branch

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CAN YOU DO IT?
❑ Assume HW forwarding and NO delay slot for load
❑ Identify all data hazards in the following instruction
sequences by circling each source register that is read
before the updated value is written back
LW R2, 0(R1)
ADDI R3, R2, 1
BEQ R2, R1, X
SW R3, 4(R1)
X: some inst

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LOAD FOLLOWED BY R-TYPE INSTRUCTION

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LOAD FOLLOWED BY R-TYPE INSTRUCTION

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LOAD FOLLOWED BY R-TYPE INSTRUCTION

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LOAD FOLLOWED BY R-TYPE INSTRUCTION

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LOAD FOLLOWED BY R-TYPE INSTRUCTION

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LOAD FOLLOWED BY R-TYPE INSTRUCTION

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HAZARD DETECTION UNIT (PARTIAL)

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PIPELINE WITH DATAPATH AND CONTROL

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LOAD FOLLOWED BY BRANCH INSTRUCTION

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 BEFORE NEXT CLASS

• H&H 8-8.3
• Next time:
Caches

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