Energy-Efficient Low-Latency 600 MHz FIR with High-Overdrive Charge-Recovery Logic

Abstract
This paper presents a 14-tap 8-bit finite impulse response (FIR) test-chip that has been designed using a novel charge-recovery logic family, called Enhanced Boost Logic (EBL), to achieve high-speed and low-power operation. Compared to previous charge-recovery circuitry, EBL achieves increased gate overdrive, resulting in low latency overhead over static CMOS design. The EBL-based FIR has been designed with only 1.5 cycles of additional latency over its static CMOS counterpart, while consuming 21% less energy per cycle, based on postlayout simulations of the two designs. The test-chip has been using FPGA.

Aim
To design Differential Coding for MAC Based Two-User MIMO Communication Systems

Objective
The objectives of this works are, 1. Design of Differential Coding for MAC Based Two-User MIMO Communication Systems using VHDL. 2. Functional verification of the above design 3. Result analysis in terms of a. Area b. Power c. Speed

Tools to be used:
For functional simulation For synthesis and implementation Mentor Graphics ModelSim 6.5 or later Xilinx Incs Xilinx ISE 13.1or later version

For FPGA based implementation, the FPGA Details are,

Manufacturer Family FPGA Series Xilinx Spartan 3/Spartan 3E XC3S400PQ208/XC3S250EPQ208

For CPLD based implementation, the CPLD Details are,

Manufacturer Family CPLD Series Xilinx XC9500 XC9572-XL

HDL to be used:
VHDL/Verilog HDL

Project Report Details:

Soft copy of documents referred by our guide to do the project will be given to prepare the report.